Renesas RL78/G1D User Manual

RL78/G13 CHAPTER 11 A/D CONVERTER
R01UH0146EJ0100 Rev.1.00 520
Sep 22, 2011
11.7.1 Setting up software trigger mode
Figure 11-32. Setting up Software Trigger Mode
Start of setup
PER0 register setting
ADPC and PMC register settings
PM register setting
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
(The order of the settings is
irrelevant.)
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to analog input.
ANI0 to ANI14 pins: Set using the ADPC register
ANI16 to ANI26 pins: Set using the PMC register
The ports are set to the input mode.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: Sequential conversion mode/one-shot conversion mode
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
voltage source.
ADRCK bit: This is used to select the range for the A/D conversion result
comparison value generated by the interrupt signal from AREA1,
AREA3, and AREA2.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
• ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
ADCE bit setting
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D
conversion standby status.
Stabilization wait time count (1 μ s)
The software counts up to the stabilization wait time (1 μ s).
Start of A/D conversion
End of A/D conversion
The A/D conversion operations are performed.
The A/D conversion end interrupt (INTAD) is generated.
Note
Storage of conversion results in
the ADCR and ADCRH registers
The conversion results are stored in the ADCR and ADCRH registers.
ADCS bit setting
After counting up to the stabilization wait time ends, the ADCS bit of the ADM0
register is set (1), and A/D conversion starts.
Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.

Renesas RL78/G1D Specifications

General

Brand	Renesas
Model	RL78/G1D
Category	Computer Hardware
Language	English