Xilinx VCU118 User Manual

VCU118 Board User Guide 63
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-16: VCU118 FPGA U1 GTY Transceiver Bank 226 Connections
MGT
Bank
FPGA
(U1)
Pin
FPGA (U1) Pin Name
Schematic Net
Name
Connected Pin
Connected Pin
Name
Connected
Device
GTY
Bank
226
AN5 MGTYTXP0_226 PCIE_TX7_P A47 HSIP(7)
PCIe EDGE Conn.
U2
AN4 MGTYTXN0_226 PCIE_TX7_N A48 HSIN(7)
AH2 MGTYRXP0_226 PCIE_RX7_P B45 HSOP(7)
AH1 MGTYRXN0_226 PCIE_RX7_N B46 HSON(7)
AM7 MGTYTXP1_226 PCIE_TX6_P A43 HSIP(6)
AM6 MGTYTXN1_226 PCIE_TX6_N A44 HSIN(6)
AG4 MGTYRXP1_226 PCIE_RX6_P B41 HSOP(6)
AG3 MGTYRXN1_226 PCIE_RX6_N B42 HSON(6)
AK7 MGTYTXP2_226 PCIE_TX5_P A39 HSIP(5)
AK6 MGTYTXN2_226 PCIE_TX5_N A40 HSIN(5)
AF2 MGTYRXP2_226 PCIE_RX5_P B37 HSOP(5)
AF1 MGTYRXN2_226 PCIE_RX5_N B38 HSON(5)
AH7 MGTYTXP3_226 PCIE_TX4_P A35 HSIP(4)
AH6 MGTYTXN3_226 PCIE_TX4_N A36 HSIN(4)
AE4 MGTYRXP3_226 PCIE_RX4_P B33 HSOP(4)
AE3 MGTYRXN3_226 PCIE_RX4_N B34 HSON(4)
AG9 MGTREFCLK0P_226 MGT226_CLK0_P
(1)
J31 1
SMA Connectors
J31(P), J30(N)
AG8 MGTREFCLK0N_226 MGT226_CLK0_N
(1)
J30 1
AE9 MGTREFCLK1P_226 NC
AE8 MGTREFCLK1N_226 NC
BD2 MGTRREF_RS MGTRREF_226 R1088.1 100Ω 1% P/U to MGTAVTT_FPGA
BD3 MGTAVTTRCAL_RS MGTAVTT_FPGA NA NA NA
Notes:
1. Ensure that the GTY RefClock being sourced into the RefClock SMAs (J30, J31) is AC coupled for proper clocking operation of
GTY transceivers. Use inline SMA DC blocking capacitors if frequency source output is not AC coupled.
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English