Xilinx VCU118 User Manual

VCU118 Board User Guide 66
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Chapter 3: Board Component Descriptions
Table 3-19: VCU118 FPGA U1 GTY Transceiver Bank 232 Connections
MGT
Bank
FPGA
(U1)
Pin
FPGA (U1) Pin Name Schematic Net Name
Connected
Pin
Connected Pin
Name
Connected
Device
GTY
Bank
232
L5 MGTYTXP0_232 QSFP2_TX1_P 36 TX1P
QSFP2 U123
L4 MGTYTXN0_232 QSFP2_TX1_N 37 TX1N
T2 MGTYRXP0_232 QSFP2_RX1_P 17 RX1P
T1 MGTYRXN0_232 QSFP2_RX1_N 18 RX1N
K7 MGTYTXP1_232 QSFP2_TX2_P 3 TX2P
K6 MGTYTXN1_232 QSFP2_TX2_N 2 TX2N
R4 MGTYRXP1_232 QSFP2_RX2_P 22 RX2P
R3 MGTYRXN1_232 QSFP2_RX2_N 21 RX2N
J5 MGTYTXP2_232 QSFP2_TX3_P 33 TX3P
J4 MGTYTXN2_232 QSFP2_TX3_N 34 TX3N
P2 MGTYRXP2_232 QSFP2_RX3_P 14 RX3P
P1 MGTYRXN2_232 QSFP2_RX3_N 15 RX3N
H7 MGTYTXP3_232 QSFP2_TX4_P 6 TX4P
H6 MGTYTXN3_232 QSFP2_TX4_N 5 TX4N
M2 MGTYRXP3_232 QSFP2_RX4_P 25 RX4P
M1 MGTYRXN3_232 QSFP2_RX4_N 24 RX4N
R9 MGTREFCLK0P_232 MGT_SI570_CLOCK2_C_P 13 Q2_P
U104 SI53340
clock buffer
R8 MGTREFCLK0N_232 MGT_SI570_CLOCK2_C_N 14 Q2_N
N9 MGTREFCLK1P_232 SI5328_CLOCK2_C_P 35 CLKOUT2_P
U57 SI5328B
jitter atten.
N8 MGTREFCLK1N_232 SI5328_CLOCK2_C_N 34 CLKOUT2_N
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English