Theory of Operation: Controller 3-33
3.2.4.8.2 Audio SSI
OMAP's McBSP1 interface is configured as a SSI interface dedicated to carry transmit and receive
audio data to peripheral devices. The peripherals connected to this bus include MAKO, Audio
CODEC, MACE and CPLD. MAKO generates the clock and frame sync signals for this bus.
Figure 3-25. Audio SSI Configuration
3.2.4.8.3 ARM SPI
This SPI interface is controlled by OMAP's ARM core. Devices connected to this bus include MAKO,
display controllers and the audio CODEC.
3.2.4.8.4 DSP SPI
This SPI interface is controlled by the DSP core of the OMAP processor. This bus is used to
configure and control devices on the RF deck.
OMAP
MACE
MCBSP1
SSC 0
(Black)
SSC 1
( Red )
BLACK or
RED RX
RED RX
RED TX
CODECs
CPLD
BLACK or
RED TX
0
0
1
1
Mux A
PA 28 (GPIO)
Hi_Sec */Normal
SSC 2
(Sniffer)
RD 2
RD 0
TD 0
RD 1
TD 1
TD 3
Mux B
Main Board
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