Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1218
Dec 10, 2015
17.4.6 Error Status
(1) LIN Master Mode
(a) Types of Error Statuses
The LIN/UART module can detect six types of error statuses in LIN master mode. The condition of these error
statuses can be checked by means of the corresponding bits in the LESTn register.
All error statuses represent interrupt events.
Table 17-16 shows the types of error statuses.
Table 17-16. Types of Error Statuses in LIN Master Mode
Status Error detection condition
Operation mode
capable of error
detection
Communication
Enable/disable
detection
Corresponding
bit
Bit error The transmitted data and the data on the
LIN bus monitored by the receive pin do not
match
Note 1, 2
 LIN operation
mode
 LIN wake-up
mode
Cancel O
BER flag in
LESTn register
Physical bus
error
 LIN bus is detected to be high when
sending a break
 LIN bus is detected to be low when
sending a break delimiter
 LIN bus is detected to be high when
sending a wake-up
 LIN operation
mode
 LIN wake-up
mode
Cancel O
PBER flag in
LESTn register
Timeout error A frame or response transmission/reception
does not terminate within a given time
Note 3
LIN operation
mode
Cancel O
FTER flag in
LESTn register
Framing error In response field reception, a stop bit of
each data byte is low
LIN operation
mode
Cancel O
FER flag in
LESTn register
Checksum
error
In response field reception, the result of
checksum test gives an error
LIN operation
mode
— ×
CSER flag in
LESTn register
Response
preparation
error
The following conditions occur in frame
separate mode:
 The first reception data byte is received
after completion of header transmission
but before a response
transmission/reception request is set
 The first reception data byte is received
after completion of the previous data
group reception but before a
transmission/reception request for
another data group is set
LIN operation
mode
Cancel ×
RPER flag in
LESTn register
Notes 1. If a bit error is detected, the process is canceled after a stop bit is sent. If a bit error is detected in a non-
data area, such as an inter-byte space, the transmission is canceled immediately after transmission of error
bit. If a bit error is detected during the transmission of a wake-up, the transmission of the wake-up is
canceled after the error-causing bit is sent.
2. In multi-byte response transmission, a bit error can be detected between data groups.
3. The timeout time depends on the response field data length (the RFDL[3:0] bits in the LDFCn register) and
the checksum selection (the CSM bit in the LDFCn register), and this can be calculated according to the
following formula:
Timeout time is 8 data bytes until setting of LTRCn register in frame separate mode (FSM bit of LDFCn
register is set to 1).
[Frame timeout]
 On classic selection (when the CSM bit in the LDFCn register is 0):
Timeout time = 49 + (number of data bytes + 1) × 14 [Tbit]
 On enhanced selection (when the CSM bit in the LDFCn register is 1):
Timeout time = 48 + (number of data bytes + 1) × 14 [Tbit]
<R>
<R>

Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English