RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 394
Dec 10, 2015
5.3.15 fMP Clock Division Register (MDIV)
This register is used to divide the frequency of the f
MP clock (1/2, 1/4, 1/8, 1/16, 1/32, or 1/64).
Set the MDIV register by an 8-bit memory manipulation instruction.
Writing to the MDIV register is disabled when the GCSC bit of the IAWCTL register is set to 1.
Figure 5-22. Format of f
MP Clock Division Register (MDIV)
Address: F02C7H After reset: 00H/01H
Note
R/W
Symbol 7 6 5 4 3 2 1 0
MDIV 0 0 0 0 0 MDIV2 MDIV1 MDIV0
MDIV2 MDIV1 MDIV0
0 0 0 Selects fMP.
0 0 1 Selects fMP/2.
0 1 0 Selects fMP/4.
0 1 1 Selects fMP/8.
1 0 0 Selects fMP/16.
1 0 1 Selects fMP/32.
1 1 0 Selects fMP/64.
Other than above Setting prohibited
Note The value of the FRQSEL4 bit in the user option byte (000C2H/020C2H) becomes the initial
value of the MDIV0 bit in the MDIV register.
Cautions 1. When setting the MDIV register, make the frequency after division of f
MP be within
the range of 1 MHz to 32 MHz (or 1 MHz to 24 MHz for grade-K and grade-Y products).
2. When FRQSEL4 = 1 in the user option byte (000C2H/020C2H), set the MDIV2 to
MDIV0 bits to 001 (division by 2). Setting these bits to 001 (division by 2) is
unnecessary in the clock through mode by PLL oscillation stop detection.
3. When the PLLDIV1 bit in the PLLCTL register is 1 (f
PLL  32 MHz), set the MDIV2 to
MDIV0 bits to 001 (division by 2). Setting these bits to 001 (division by 2) is
unnecessary in the clock through mode by PLL oscillation stop detection.
4. When 64 MHz or 48 MHz is selected as f
IH, the initial setting of the MDIV register is
"division by 2" so that f
CLK is set to 32 MHz or 24 MHz, respectively.
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