RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 467
Dec 10, 2015
6.3.18 PWM output delay control register 2 (PWMDLY2)
This register controls output delay of PWM output signal output from the TO1n pin.
Set the PWMDLY2 register by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Address: F022DH After reset: 00H R/W
Symbol 15 14 13 12 11 10 9 8
PWMDLY2 TO171 TO170 TO161 TO160 TO151 TO150 TO141 TO140
Address: F022CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PWMDLY2 TO131 TO130 TO121 TO120 TO111 TO110 0 0
TO1n1 TO1n0 PWM output delay control of timer array unit 1 TO1n
0 0 No delay
0 1 Delayed by one cycle of the CPU/peripheral hardware clock (fCLK).
1 0 Delayed by two cycles of the CPU/peripheral hardware clock (fCLK).
1 1 Delayed by three cycles of the CPU/peripheral hardware clock (fCLK).
Remarks 1. n: Channel number (n = 1 to 7)
2. Bits 15 to 0 are not provided in the Group A products.
Bits 15 to 8 are not provided in the Group B, C, and D products.
Cautions 1. Set this register before outputting a PWM output signal (do not change the setting during operation).
2. Set this register with a 16-bit memory manipulation instruction. Do not set this register with a 1-bit
or 8-bit memory manipulation instruction.
3. If this register is not used for PWM output, it should be cleared to 0. This is because the timer
output is delayed.
4. When setting this register after the PWM output is stopped, wait for four cycles of the
CPU/peripheral hardware clock (f
CLK) before the setting.
5. Even if this register is set for a delay, this doesn’t affect the operation of other pin functions
multiplexed on the same pin as the TO1n pin function (n = 1 to 7).
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