Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 650
Dec 10, 2015
8.5.3 Count Source
 Switch the count source after the count stops.
[Changing procedure]
(1) Set the TSTARTi bit (i = 0 or 1) in the TRDSTR register to 0 (count stops).
(2) Change bits TCK0 to TCK2 in the TRDCRi register.
 When selecting the count source for the timer RD, set the same clock source as the count source for f
CLK before setting
bit 4 (TRD0EN) in the peripheral enable register 1 (PER1).
8.5.4 Input Capture Function
 Set the pulse width of the input capture signal to three or more cycles of the timer RD operating clock (fTRD).
 The value of the TRDi register is transferred to the TRDGRji register two to three cycles of the timer RD operating clock
(f
TRD) after the input capture signal is applied to the TRDIOji pin (i = 0 or 1, j = A, B, C, or D) (when no digital filter is
used).
 In input capture mode, an input capture interrupt request for the active edge of the TRDIOji input is also generated
when the TRDTSTARTi bit in the TRDSTR register is 0 (count stops) if the edge selected by bits TRDIOj0 and TRDIOj1
in the TRDIORji register is input to the TRDIOji pin (i = 0 or 1; j = A, B, C, or D). Set the pulse width of the input capture
signal to three or more cycles of the timer RD operating clock (f
TRD).
8.5.5 Procedure for Setting Pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi (i = 0 or 1)
After a reset, the I/O ports multiplexed with pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi function as input ports.
To output from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi, use the following setting procedure:
Changing procedure
(1) Set the mode and the initial value.
(2) Enable output from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi (TRDOER1 register).
(3) Set the port register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi to 0.
(4) Set the port mode register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi to output mode.
(Output is started from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi)
(5) Start the count (set bits TSTART0 and TSTART1 to 1).
To change the port mode register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi from output
mode to input mode, use the following setting procedure:
(1) Set the port mode register bits corresponding to pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi to input mode (input
is started from pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi).
(2) Set to the input capture function.
(3) Start the count (set bits TSTART0 and TSTART1 to 1).
When switching pins TRDIOAi, TRDIOBi, TRDIOCi, and TRDIODi from output mode to input mode, input capture
operation may be performed depending on the pin states. When the digital filter is not used, edge detection is performed
after two or more cycles of the timer RD operating clock (f
TRD) have elapsed. When the digital filter is used, edge detection
is performed after five or more cycles of the sampling clock have elapsed.
8.5.6 External clock TRDCLK0
Set the pulse width of the external clock applied to the TRDCLK0 pin to three or more cycles of the timer RD operating
clock (f
TRD).

Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English