Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 409
Dec 10, 2015
5.6.6 CPU Clock Status Transition Diagram
Figure 5-27 shows the CPU clock status transition diagram of this product.
Figure 5-27. CPU Clock Status Transition Diagram
Caution Transitions in the order of (B)  (D)  (C) or (C)  (D)  (B) are prohibited.
The following shows an example of changing the CPU clock and setting the SFR register.
(1) After reset release (A), change the CPU to operating with the high-speed on-chip oscillator clock (B).
(A)(B): Setting the SFR register is not required (initial status after reset release).
(2) Change the CPU from operating with the high-speed on-chip oscillator clock (B) to operating with the high-
speed system clock (C).
 Set the CMC register (EXCLK = 0, OSCSEL = 1, AMPH = x).
Note 1
 Set the OSTS register.
Note 2
 Set the MSTOP bit of the CSC register to 0.
 Check the oscillation stabilization time by using the OSTC register.
Note 2
 Set the MCM0 bit of the CKC register to 1.
 Set the MCS bit of the CKC register to 1.
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
2. Set the oscillation stabilization time of the oscillation stabilization time select register (OSTS) as shown below:
OSTS register setting value ≥ Expected oscillation stabilization time counter status register (OSTC)
Power ON
Reset release
V DD ≥ 2.7 V
High-speed on-chip oscillator: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
(B)
(A)
(C)
(D)
(E)
(F)
(G)
(N)
(M)
(H)
(J)
(I)
(K)
(L)
V DD ≥ 1.56 V (Typ.)
V
DD ≥ 1.56 V (Typ.)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
XT1 oscillation/EXCLKS input: Stops (input port mode)
CPU: Operating
with high-speed
on-chip oscillator
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Selectable by CPU
XT1 oscillation/EXCLKS input: Selectable by CPU
CPU: High-speed
on-chip oscillator
→ STOP
CPU: High-speed
on-chip oscillator
→ HALT
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Oscillatable
XT1 oscillation/EXCLKS input:
Oscillatable
CPU: Operating
with X1 oscillation or
EXCLK input
CPU: X1
oscillation/EXCLK
input → STOP
CPU: X1
oscillation/EXCLK
input → HALT
CPU: XT1
oscillation/EXCLKS
input → HALT
CPU: Low-speed
on-chip oscillator
→ HALT
CPU: Operating
with low-speed
on-chip oscillator
High-speed on-chip oscillator:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: PLL operating
(CLS, MCM0 = 0, 1)
→ HALT
CPU: Operating
with PLL (CLS,
MCM0 = 0, 1)
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Oscillatable
XT1 oscillation/EXCLKS input: Operating
CPU: Operating with
XT1 oscillation/EXCLKS input
XT1 oscillation/EXCLK input
High-speed on-chip oscillator: Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Oscillatable
CPU: High-speed
on-chip oscillator
→ SNOOZE
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Oscillatable

Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English