RL78/F13, F14 CHAPTER 25 POWER-ON-RESET CIRCUIT
R01UH0368EJ0210 Rev.2.10 1555
Dec 10, 2015
CHAPTER 25 POWER-ON-RESET CIRCUIT
25.1 Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the following functions.
ï‚· Generates internal reset signal at power on.
The reset signal is released when the supply voltage (V
DD) exceeds 1.56 V (typ.).
ï‚· Compares supply voltage (V
DD) and detection voltage (VPDR = 1.55 V (typ.)), generates internal reset signal when VDD
< V
PDR.
Caution If an internal reset signal is generated in the POR circuit, the POCRES_0 and CLKRF flags of the
POR/CLM reset confirmation register (POCRES) and the TRAP, WDCLRF, IAWRF, and LVIRF flags
of the reset control flag register (RESF) are cleared (00H).
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset source is located in the RESF and POCRES registers for when an internal reset signal
is generated by the power-on reset (POR), watchdog timer (WDT), clock monitor, voltage detector (LVD),
illegal instruction execution, or illegal-memory access. The RESF register is not cleared to 00H and the
flag is set to 1 when an internal reset signal is generated by the watchdog timer (WDT), voltage detector
(LVD), illegal instruction execution, clock monitor, or illegal-memory access. The POCRES register is not
cleared to 00H and the flag is set to 1 when an internal reset signal is generated by the clock monitor.
For details of the POCRES and RESF registers, see CHAPTER 24 RESET FUNCTION.
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