RL78/F13, F14 CHAPTER 7 TIMER RJ
R01UH0368EJ0210 Rev.2.10 563
Dec 10, 2015
7.4.7 Coordination with Event Link Controller (ELC)
The ELC is only available in the RL78/F14.
Through coordination with the ELC, event input from the ELC can be set to be the count source. Bits TCK0 to TCK2 in
the TRJMR0 register count at the rising edge of event input from the ELC. However, ELC input does not function in event
counter mode.
The ELC setting procedure is shown below:
• Procedure for starting operation
(1) Set the event output destination select register (ELSELRn) for the event link controller (ELC).
(2) Set the operating mode for the event generation source.
(3) Set the mode for timer RJ.
(4) Start the count operation of timer RJ.
(5) Start the operation of the event generation source.
• Procedure for stopping operation
(1) Stop the operation of the event generation source.
(2) Stop the count operation of timer RJ.
(3) Set the event output destination select register (ELSELRn) for the event link controller (ELC) to 0.
7.4.8 Output Settings for Each Mode
Table 7-6 and Table 7-7 list the states of pins TRJO0 and TRJIO0 in each mode.
Table 7-6. TRJO0 Pin Setting
Operating Mode TRJIOC0 Register TRJO0 Pin Output
TOENA Bit TEDGSEL Bit
All modes 1 1 Inverted output
0 Normal output
0 0 or 1 Output disabled
Table 7-7. TRJIO0 Pin Setting
Operating Mode TRJIOC0 Register TRJIO0 Pin I/O
PMXX Bit
Note
TEDGSEL Bit
Timer mode 0 or 1 0 or 1 Input (Not used)
Pulse output mode 1 0 or 1 Output disabled
(Hi-z output)
0 1 Normal output
0 Inverted output
Event counter mode 1 0 or 1 Input
Pulse width measurement mode
Pulse period measurement mode
Note The port mode register (PMxx) bit corresponding to port multiplexed with TRJIO0 function.
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