Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 1 OVERVIEW
R01UH0368EJ0210 Rev.2.10 12
Dec 10, 2015
1.4.3 RL78/F14: Block Diagram of R5F10PLn (n = G, H, J) 64-pin Products
Figure 1-3. Block Diagram
4
8
13
20
TI00
TO00
TI01
TO01
TI02
TO02
TI03
TO03
TI04
TO04
TI05
TO05
TI06
TO06
TI07
TO07
TRDIOB0
TRDIOA0/TRDCLK0
TRDIOC0
TRDIOD0
TRDIOA1
TRDIOB1
TRDIOC1
TRDIOD1
RXD0
TXD0
SCK00
SI00
SO00
SSI00
SCK01
SI01
SO01
SSI01
SCL00
SDA00
SCL01
SDA01
LRXD0
LTXD0
LIN0
(1ch)
CSI01
IIC01
IIC00
CSI00
UART0
SAU0 (2ch)
TRJ
ch1
ch0
TRD (2ch)
TAU0 (8ch)
ch00
ch01
ch02
ch03
ch04
ch05
ch06
ch07
PORT0 P00
P10 to P17PORT1 8
P30 to P34
PORT3 5
P40 to P43
PORT4 4
P50 to P53
PORT5 4
P60 to P63
PORT6 4
P70 to P77
PORT7 8
P80 to P87
PORT8 8
P90 to P96
PORT9 7
P120, P125
PORT12
P121 to P124
P130
PORT13
P137
P140PORT14
PCLBUZ0PCL/BUZ
KR0 to KR7
KEY RETURN
(8ch)
External INT
(13ch)
RTC
10-bit ADC
(20ch)
INTP0 to INTP12
RTC1HZ
ANI0 to ANI16,
ANI24 to ANI26
AV
REFP
AVREFM
SCLA0
SDAA0
IICA0
(1ch)
CRC
REGC
Voltage
REGULATOR
PLL
CLM
Main OSC
X1
XT1
X2/EXCLK
XT2/EXCLKS
TOOL
RXD
TOOL
TXDTOOL0
OCD
BCD
INT
DTC
RAM
WWDT
RESET
High-speed
OCO
Low-speed
OCO
POR/
LVD
Clock Generator
+
Reset Generator
RL78
CPU CORE
Multiplier,
Divider and
Multiply-
Accumulator
CODE FLASH
DATA FLASH
Low-speed
OCO (for WDT)
Sub OSC
TI10
TO10
TI11
TO11
TI12
TO12
TI13
TO13
TAU1 (8ch)
ch10
ch11
ch12
ch13
RXD1
TXD1
SCK10
SI10
SO10
SSI10
SCK11
SI11
SO11
SSI11
SCL10
SDA10
SCL11
SDA11
CSI11
IIC11
IIC10
CSI10
UART1
SAU1 (2ch)
CAN
(1ch)
CRXD0
CTXD0
ELC
Comparator 0
(1ch)
ANO0
IVCMP01
IVCMP00
VCOUT0
IVCMP02
IVCMP03
IVREF0
8-bit DAC
(1ch)
TI14
TO14
TI15
TO15
TI16
TO16
TI17
TO17
ch14
ch15
ch16
ch17
LRXD1
LTXD1
LIN1
(1ch)
Cautions 1. Do not use the XT1 and XT2 pin functions in grade-Y products.
TRJO0
TRJIO0
2
RESOUT
STOPST
8
SNZOUT0 to SNZOUT7
STANDBY
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Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English