RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1392
Dec 10, 2015
18.6.3 Transmission Using FIFO Buffers
Messages of a volume of the FIFO buffer depth set by the CFDC[2:0] bits in the CFCCLk register can be stored in a
single transmit/receive FIFO buffer. Messages are transmitted sequentially on a first-in, first-out basis.
Transmit/receive FIFO buffers are linked to transmit buffers selected by the CFTML[1:0] bits in the CFCCHk register.
When the CFE bit in the CFCCLk register is set to 1 (transmit/receive FIFO buffers are used), transmit/receive FIFO
buffers become targets of transmit priority determination. Priority determination is made for only the message to be
transmitted next in a FIFO buffer.
When the CFE bit is set to 0 (no transmit/receive FIFO buffer is used), the CFEMP flag is set to 1 (the transmit/receive
FIFO buffer contains no message (buffer empty)) at the timing below.
• The transmit/receive FIFO buffer becomes empty immediately when the message in it is not being transmitted
or is not to be transmitted next.
• The transmit/receive FIFO buffer becomes empty after transmission completion, CAN bus error detection, or
arbitration lost when the message in it is being transmitted or to be transmitted next.
When the CFE bit is cleared to 0, all messages in transmit/receive FIFO buffers are lost and messages cannot be
stored in FIFO buffers. Confirm that the CFEMP flag is set to 1 before setting the CFE bit to 1 again.
(1) Interval Transmission Function
To transmit messages from the same FIFO buffer while a transmit/receive FIFO buffer that is set to transmit mode is in
use, message transmission interval time can be set.
Immediately after the first message has been transmitted successfully from the FIFO buffer with the CFE bit in the
CFCCLk register set to 1, the interval timer starts counting (after EOF7 of the CAN protocol). After that, when the interval
time has passed, the next message is transmitted. The interval timer stops in channel reset mode or by clearing the CFE
bit to 0.
The interval time is set by the CFITT[7:0] bits in the CFCCHk register. When the interval timer is not used, set the
CFITT[7:0] bits to H'00.
Select an interval timer count source by the CFITR and CFITSS bits in the CFCCHk register. When the CFITR and
CFITSS bits are set to B'00, the clock obtained by frequency-dividing f
CLK/2 by the ITRCP[15:0] value is used as a count
source. When the CFITR and CFITSS bits are set to B'10, the clock obtained by frequency-dividing f
CLK/2 by the
ITRCP[15:0] value × 10 is used as a count source. When the CFITR and CFITSS bits are set to B'x1, the CANi bit time
clock is used as a count source.
The interval time is calculated by the following equations where M is the set ITRCP[15:0] value and N is the set
CFITT[7:0] value.
1. When CFITR and CFITSS = B’00
2. When CFITR and CFITSS = B’10
3. When CFITR and CFITSS = B’x1 (f
CANBIT is CANi bit time clock frequency)
1
× 2 × M × N
f
CLK
1
× 2 × M × 10 × N
fCLK
1
× N
f
CANBIT
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