RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1425
Dec 10, 2015
18.14 Notes on the CAN Module
•
When changing a global mode, check the GSLPSTS, GHLTSTS, and GRSTSTS flags in the GSTS register for
transitions. When changing a channel mode, check the CSLPSTS, CHLTSTS, and CRSTSTS flags in the
CiSTSL register for transitions.
• The acceptance filter processing checks receive rules sequentially in ascending order from the minimum rule
number. If the same ID, IDE bit, or RTR bit value is set for multiple receive rules, the minimum number of
receive rule is used for the acceptance filter processing. If the message does not pass through the subsequent
DLC filter processing, the data processing is terminated without returning to the acceptance filter processing
and the message is not stored in the buffer.
• When linking transmit buffers to transmit/receive FIFO buffers, set the control register (TCMp) of the
corresponding transmit buffer to H'00. The status register (TMSTSp) of the corresponding transmit buffer should
not be used. Flags in other status registers (registers TMTRSTS, TMTCSTS, and TMTASTS), which correspond
to transmit buffers linked to transmit/receive FIFO buffers remain unchanged. Set the enable bit in the
corresponding interrupt enable register (the TMIEC register) to 0 (transmit buffer interrupt is disabled).
• When the CANi bit time clock is selected as a timestamp counter clock source, the timestamp counter stops
when the corresponding channel has transitioned to channel reset mode or channel halt mode.
• In case of an attempt to store a new receive message when the receive FIFO buffer and the transmit/receive
FIFO buffer are full, the new message is discarded. If you wish to store a new transmit message in the
transmit/receive FIFO buffer, check that the transmit/receive FIFO buffer is not full.
• Since an interrupt request flag in the CAN module is not automatically cleared to 0 when an interrupt is
accepted, the flags must be cleared to 0 by software. After the corresponding interrupt request flag has been set
to 1, an interrupt is not generated even if an interrupt source condition is satisfied.
• In order to generate the CAN related interrupt that several interrupt sources are gathered, the following
condition should be met:
All interrupt request flags corresponding to these interrupt sources in the CAN module are set to 0 (note that this
only applies to those interrupt request flags for which the corresponding interrupt enable bits shown in Table 18-
12 are set to 1).
• The values of unused CAN receive buffer registers (RMIDLn, RMIDHn, RMTSn, RMPTRn, and RMDF0n to
RMDF3n), CAN receive FIFO access registers (RFIDLm, RFIDHm, RFTSm, RFPTRm, and RFDF0m to
RFDF3m), and CANi transmit/receive FIFO access registers (CFIDLk, CFIDHk, CFTSk, CFPTRk, and CFDF0k
to CFDF3k) become undefined once the CAN module exits from global reset mode and enters global operation
mode or global test mode.
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