Renesas RL78/D1A User Manual

RL78/F13, F14 CHAPTER 17 LIN/UART MODULE (RLIN3)
R01UH0368EJ0210 Rev.2.10 1255
Dec 10, 2015
17.7.3 UART Mode
Figure 17-43 shows a block diagram of baud rate generation in UART mode.
Figure 17-43. Block Diagram of Baud Rate Generation in UART Mode
Set the LIN communications clock source as follows.
 LIN communications clock source = f
CLK
Note1
 In the range from 4 MHz to 32 MHz
Note 1. It is available to select the f
MX to the LIN communications clock source. In that case, set at least 1.2 times the
frequency of the LIN communication clock source to the CPU/peripheral hardware clock(fCLK).
Table 17-30. UART Baud Rate Setting Examples (when LIN communication clock source = 32 MHz)
UART Baud
Rate (Target
Baud Rate)
Prescaler
Baud rate generator 0-1
N+1 frequency-divided
Baud rate Error
1200 bps 1/2 833 1200.48 +0.04%
2400 bps 1/2 417 2398.08 -0.08%
4800 bps 1/2 208 4807.69 +0.16%
9600 bps 1/2 104 9615.38 +0.16%
19200 bps 1/2 52 19230.77 +0.16%
31250 bps 1/2 32 31250.00 0.00%
38400 bps 1/2 26 38461.54 +0.16%
Remarks 1. These examples are for sixteen samples per bit (i.e. when NSPB[3:0] = 0000b or 1111b).
2. The baud rate can be calculated by the following expression.
Baud rate = (LIN communications clock source (f
CLK or fMX: selected by the LINnMCK bits) frequency)
× (frequency divider selected by LPRS[2:0] ÷ (LBRPn0 + (0x0100 × LBRPn1) + 1))
 number selected by NSPB[3:0] bps
Note For the LIN communication clock source, refer to CHAPTER 5 CLOCK GENERATOR.
LIN communication
clock source
Note
Prescaler clock
f
LIN
Baud rate generator
Prescaler
(LPRS[2:0] bits)
16-bit counter
b15 b0
LBRPn1
register
LBRPn0
register
LIN baud rate prescaler
(LBRPn0 and LBRPn1
registers)
Baud rate
fa
Bit sampling
1/6 to 1/16
(NSPB[3:0] bits)
<R>

Renesas RL78/D1A Specifications

General

Brand	Renesas
Model	RL78/D1A
Category	Computer Hardware
Language	English