RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1414
Dec 10, 2015
(7) The message is stored in the transmit/receive FIFO buffer set in receive mode, when the message has passed
through the DLC filter process if the CFE bit is set to 1 (transmit/receive FIFO buffers are used) and the CFDC[2:0]
bits are set to B'001 or more.
The CFMC[5:0] value is incremented to H'01. When the CFIM bit is set to 1 (an interrupt occurs each time a
message has been received), the CFRXIF flag is set to 1 (a transmit/receive FIFO receive interrupt request is
present).
The message is stored in the receive FIFO buffer, if the RFE bit in the RFCCm register is set to 1 (receive FIFO
buffers are used) and RFDC[2:0] bits in the RFCCm register are set to B'001 or more.
The RFMC[5:0] value in the RFSTSm register is incremented to H'01. When the RFIM bit in the RFCCm register is
set to 1 (an interrupt occurs each time a message has been received), the RFIF flag in the RFSTSm register is set
to 1 (a receive FIFO interrupt request is present).
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