RL78/F13, F14 CHAPTER 12 A/D CONVERTER
R01UH0368EJ0210 Rev.2.10 752
Dec 10, 2015
12.7.4 Setup when using temperature sensor (example for software trigger mode and one-shot conversion mode)
Figure 12-37. Setup When Using Temperature Sensor
Note Depending on the settings of the ADRCK bit and ADUL/ADLL registers, there is a possibility of no interrupt signal
being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
PER0 register setting
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
The ADCEN bit of the PER0 register is set (1), and supplying the clock
starts.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D
conversion time.
ADMD bit: This is used to specify the select mode.
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software
trigger mode.
ADSCM bit: One-shot conversion mode
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the
reference voltage source.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion
result comparison values.
• ADS register
ADISS and ADS4 to ADS0 bits: These are used to select temperature
sensor output or internal reference
voltage output.
ADCE bit setting
The ADCE bit of the ADM0 register is
set (1), and the system enters the
A/D conversion standby status.
Stabilization wait time count B
First A/D
conversion time
Second A/D
conversion time
If a temperature sensor output/internal reference voltage output (ADISS
bit of ADS register = 1) is selected as the analog input channel: B = 1 µs
Start of A/D conversion
End of A/D conversion
The A/D conversion end interrupt (INTAD) is generated.
Note
The conversion results are stored in the ADCR and ADCRH registers.
ADCS bit setting
After counting up to the stabilization wait time B ends, the ADCS bit of the
ADM0 register is set (1), and A/D conversion starts.
Storage of conversion results in
the ADCR and ADCRH registers
End of A/D conversion
Start of setup
The A/D conversion end interrupt (INTAD) will be generated.
After ADISS is set (1), the initial conversion result cannot be used.
The ADCS bit of the ADM0 register is set (1), and A/D conversion starts.
Start of A/D conversion
ADRCK bit: This is used to select the range of values for comparison with the result of
A/D conversion in the generation of interrupt signals in response to results
being in either area 1 or areas 3 and 2.
Waiting for the time indicated by A below may be required for the results of conversion to become
stable after a change to the values of the ADREFP1 and ADREFP0 bits if the given condition holds.
A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1,
respectively.
Setting the values of ADREFP1 and ADREFP0 to 1 and 0, respectively is prohibited.
Stabilization wait time count A
ADCS bit setting
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