RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 985
Dec 10, 2015
15.8.2 LIN reception
Of UART reception, UART0 support LIN communication.
For LIN reception, channel 1 of unit 0 is used.
UART UART0 UART1
Support of LIN communication Supported Not supported
Target channel Channel 1 of SAU0
−
Pins used RxD0
−
Interrupt INTSR0
−
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag • Framing error detection flag (FEF01)
• Overrun error detection flag (OVF01)
Transfer data length 8 bits
Transfer rate Max. fMCK/6 [bps] (SDR01 [15:9] = 2 or more), Min. fCLK/(2 × 2
11
× 128) [bps]
Note
Data phase Forward output (default: high level)
Reverse output (default: low level)
Parity bit No parity bit (The parity bit is not checked.)
Stop bit The first bit is checked.
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications.
Remark fMCK: Operation clock frequency of target channel
f
CLK: System clock frequency
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