RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1405
Dec 10, 2015
Table 18-13. Example of Bit Timing Setting
1 Bit
Set Value (Tq)
Sample Point (%)
Note: See Figure 18-17.
SS TSEG1 TSEG2 SJW
8 Tq 1 4 3 1 62.50
1 5 2 1 75.00
10 Tq 1 6 3 1 70.00
1 7 2 1 80.00
16 Tq 1 10 5 1 68.75
1 11 4 1 75.00
20 Tq 1 13 6 1 70.00
1 15 4 3 80.00
24 Tq 1 15 8 1 66.67
1 16 7 1 70.83
18.10.3 Communication Speed Setting
Set the CAN communication speed for each channel using the f
CAN, baud rate prescaler division value (BRP[9:0] bits in
the CiCFGL register), and Tq count per bit time.
Figure 18-18 shows the CAN clock control block diagram, and Table 18-14 shows an example of the communication
speed setting.
Figure 18-18. CAN Clock Control Block Diagram
Notes 1. If the high-speed on-chip oscillator clock (fIH) or the PLL clock with its source as the high-speed
on-chip oscillator clock is to be selected as the source of the clock signal for f
CLK, make sure that
the condition f
X < fCLK/2 is satisfied.
2. If the high-speed system clock is to be selected as f
CLK, do not select fX as fCAN.
Remark i = 0
DCS: Bit in the GCFGL register
BRP[9:0]: Bits in the CiCFGL register
f
CAN: CAN clock
f
CANTQi: CANi Tq clock
fx
f
CANTQi
0
1
DCS
Baud rate prescaler
1 / (P+1)
fCLK
P = 0 to 1023
BRP[9:0]
f
CAN
fCAN
Baud rate prescaler division value x (Tq count of 1 bit time)
Communication speed =
Caution When fx is to be selected, the following condition must be satisfied.
fX ≤
fCLK
2
1/2
Notes 1, 2
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