Renesas RL78/F14 User Manual

RL78/F13, F14 CHAPTER 7 TIMER RJ
R01UH0368EJ0210 Rev.2.10 564
Dec 10, 2015
7.5 Notes on Timer RJ
7.5.1 Count Operation Start and Stop Control
 When event counter mode is set or the count source is set to other than the ELC
After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF bit in the
TRJCR0 register remains 0 (count stops) for three cycles of the count source. Do not access the registers associated with
timer RJ
Note
other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for three cycles of
the count source. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers associated with timer
RJ
Note
other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. Refer to CHAPTER 21 INTERRUPT
FUNCTIONS for details.
Note Registers associated with timer RJ: TRJ0, TRJCR0, TRJIOC0, TRJMR0, and TRJISR0
 When event counter mode is set or the count source is set to the ELC
After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF bit in the
TRJCR0 register remains 0 (count stops) for two cycles of the CPU clock. Do not access the registers associated with timer
RJ
Note
other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for two cycles of the
CPU clock. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers associated with timer RJ
Note
other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TSTART bit from 0 to 1. Refer to CHAPTER 21 INTERRUPT FUNCTIONS
for details.
The ELC is only available in the RL78/F14.
Note Registers associated with timer RJ: TRJ0, TRJCR0, TRJIOC0, TRJMR0, and TRJISR0
7.5.2 Access to Flags (Bits TEDGF and TUNDF in TRJCR0 Register)
Bits TEDGF and TUNDF in the TRJCR0 register are set to 0 by writing 0 by a program, but writing 1 to these bits has no
effect. If a read-modify-write instruction is used to set the TRJCR0 register, bits TEDGF and TUNDF may be erroneously
set to 0 depending on the timing, even when the TEDGF bit is set to 1 (active edge received) and the TUNDF bit is set to 1
(underflow) during execution of the instruction. Use an 8-bit memory manipulation instruction to access to the TRJCR0
register.
7.5.3 Access to Counter Register
When bits TSTART and TCSTF in the TRJCR0 register are both 1 (count starts), allow at least three cycles of the count
source clock between writes when writing to the TRJ0 register successively.
7.5.4 When Changing Mode
The registers associated with timer RJ operating mode (TRJIOC0, TRJMR0, and TRJISR0) can be changed only when
the count is stopped with both the TSTART and TCSTF bits set to 0 (count stops). Do not change these registers during
count operation.
When the registers associated with timer RJ operating mode are changed, the values of bits TSTART and TCSTF are
undefined. Write 0 (no active edge received) to the TEDGF bit and 0 (no underflow) to the TUNDF bit before starting the
count.

Renesas RL78/F14 Specifications

General

Brand	Renesas
Model	RL78/F14
Category	Computer Hardware
Language	English