Renesas RL78/F14 User Manual

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1418
Dec 10, 2015
18.12.2 Procedure for Transmission from Transmit/Receive FIFO Buffers
Figure 18-29 shows the procedure for transmission from transmit/receive FIFO buffers.
Figure 18-30 shows a timing chart where messages are transmitted from the transmit/receive FIFO buffers and
transmission has been successfully completed. Figure 18-31 shows a timing chart where messages are transmitted from
the transmit/receive FIFO buffers and transmit abort has been completed.
Figure 18-29. Procedure for Transmission from Transmit/Receive FIFO Buffers
Figure 18-30. Transmit/Receive FIFO Buffer Transmission Timing Chart
(Transmission Completed Successfully)
No
Yes
Remark k = 0
Write messages when the RPAGE bit
in the GRWCR register is set to 1.
Start
Is transmit/receive FIFO buffer full?
(Is CFFLL flag in the CFSTSk register 1?)
Store messages in registers CFIDLk, CFIDHk, CFPTRk,
CFDF0k to CFDF3k.
Set the CFPCTRk register to H'FF.
End
(1) (2) (3)
SOF
(5)
0 1
(4)
12
0
1
0
H
L
1
0
1
0
1
0
Example of transmission from transmit/receive
FIFO buffer k
CAN bus
CFDC[2:0] bits
CFE bit
CFMC[5:0] bits
CFEMP flag
CFTXIF flag
[Transmit/receive FIFO buffer k]
Remark k = 0
CFDC[2:0], CFE: Bits in the CFCCLk register
CFMC[5:0], CFEMP, CFTXIF: Flags in the CFSTSk register
SOF
EOF INT
Determine next
transmit priority
CRC
delimiter
CRC
delimiter
EOF INT
Determine next
transmit priority
Determine next
transmit priority

Renesas RL78/F14 Specifications

General

Brand	Renesas
Model	RL78/F14
Category	Computer Hardware
Language	English