Renesas RL78/F14 User Manual

RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 651
Dec 10, 2015
8.5.7 Reset Synchronous PWM Mode
 When reset synchronous PWM mode is used for motor control, make sure OLS0 = OLS1.
 Set to reset synchronous PWM mode by the following procedure:
[Changing procedure]
(1) Set the TSTART0 bit in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 and CMD0 in the TRDFCR register to 00B (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 and CMD0 to 01B (reset synchronous PWM mode).
(4) Set the other registers associated with timer RD again.
8.5.8 Complementary PWM Mode
 When complementary PWM mode is used for motor control, make sure OLS0 = OLS1.
 Change bits CMD0 and CMD1 in the TRDFCR register in the following procedure.
Changing procedure: When setting to complementary PWM mode (including re-set), or changing the transfer timing from
the buffer register to the general register in complementary PWM mode.
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 and CMD0 in the TRDFCR register to 00B (timer mode, PWM mode, and PWM3 mode).
(3) Set bits CMD1 and CMD0 to 10B or 11B (complementary PWM mode).
(4) Set the registers associated with other timer RD again.
Changing procedure: When stopping complementary PWM mode
(1) Set both the TSTART0 and TSTART1 bits in the TRDSTR register to 0 (count stops).
(2) Set bits CMD1 to CMD0 to 00B (timer mode, PWM mode, and PWM3 mode).
 Do not write to the TRDGRA0, TRDGRB0, TRDGRA1, or TRDGRB1 register during operation.
When changing the PWM waveform, transfer the values written to registers TRDGRD0, TRDGRC1, and TRDGRD1 to
registers TRDGRB0, TRDGRA1, and TRDGRB1 using the buffer operation.
However, to write data to the TRDGRD0, TRDGRC1, or TRDGRD1 register, set bits TRDBFD0, TRDBFC1, and
TRDBFD1 to 0 (general register). After this, bits TRDBFD0, TRDBFC1, and TRDBFD1 may be set to 1 (buffer register).
The PWM period cannot be changed.
 If the value set in the TRDGRA0 register is assumed to be m, the TRD0 register counts m - 1, m, m + 1, m, m - 1, in
that order, when changing from increment to decrement operation.
When changing from m to m + 1, the IMFA bit in the TRDSRi register is set to 1. Also, bits CMD1 and CMD0 in the
TRDFCR register are set to 11B (complementary PWM mode, buffer data transferred at compare match between
registers TRD0 and TRDGRA0), the content of the buffer registers (TRDGRD0, TRDGRC1, and TRDGRD1) is
transferred to the general registers (TRDGRB0, TRDGRA1, and TRDGRB1).
During operation of m + 1, m, and m - 1, the IMFA bit remains unchanged and data is not transferred to registers such
as the TRDGRA0 register.

Renesas RL78/F14 Specifications

General

Brand	Renesas
Model	RL78/F14
Category	Computer Hardware
Language	English