RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1383
Dec 10, 2015
(1) Channel Stop Mode
In channel stop mode, clocks are not supplied to channels and therefore power consumption is reduced. CAN registers
can be read, but writing data to them is prohibited. Register values are retained.
Each channel enters channel stop mode after the operation of the CAN module is enabled. The channel transitions to
channel stop mode when the CSLPR bit in the CiCTRL register is set to 1 (channel stop mode) in channel reset mode.
The CSLPR bit should not be modified in channel communication mode and channel halt mode.
(2) Channel Reset Mode
In channel reset mode, channel settings are performed. When a channel transitions to channel reset mode, some
channel-related registers are initialized. Table 18-9 lists the registers to be initialized.
When the CHMDC[1:0] bits in the CiCTRL register are set to B'01 (channel reset mode) during CAN communication,
communication is terminated before it is completed and the channel transitions to channel reset mode. Table 18-8 shows
the operation when the CHMDC[1:0] bits are set to B'01 (channel reset mode) during CAN communication.
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