AWVG7 module theory of operation
AWVG7 module t
heory of operation
This section
describes the basic operation of the major circuit blocks in the
AWVG7 module.
Bus interface
This block provides the communication b etween the mainframe and the module
circuit.
Line memory
Line memory holds the actual sample points which define a digital signal.
Address generator
This block consists of a frame delay, an MPU interface, a sequencer, an SDRAM
controll
er, and a blanking data generator. It interfaces the Frame Memory and
the Line Memory and controls the output sequence of the video data in these
memories.
Frame memory
Frame m
emory contains a series of pointers that control the order the video lines
stored in the Line Memory are used to produce digital signals.
Overlay controller
This block consists of an MPU interface and an overlay controller. It inserts data
from
the Overlay Memory into the Line Memory data stream to create circular
patterns, ID text, and logo.
Overlay memory
Overlay memory generates timings to multiplex the line memory data and the
ove
rlay data used for a circle, ID te xt, and logo overlay.
D/A conv erter and amp
This block consists of a D/A converter, two amplifiers, and a filter. It converts
the digital data from the Overlay Controller to analog signal and reconstruct the
si
gnal for output.
TG8000 Multiformat Test Signal Generator Service Manual 7–11
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