HD3G7 module theory of operation
Converter mode
In converter mo
de, the FPGA de-serializes and de-scrambles the 1.5 GHz input
signal. Each active line from the input is used twice, to double the data rate for the
output. The lines are multiplexed into the output according to the level A or B
protocol, and then scrambled and serialized.
Clocks and frames
Generator m
ode
In generator mode, the mainframe provides three fr ame pulse signals. The actual
frame signal used is the appropriate one for the rate of the signal being generated.
The selected input frame resets the c ounters in the FPGA, establishing the correct
video tim
ing. These frames are not used in converter mode, as the converter
output is always a slightly delayed version of the input signal.
The mainf
rame also provides a 54 MHz clock for generator mode. This 54 MHz
clock drives a DDS in the FPGA to create a digitized sine wave, which is then
applied to the flexible generator clock circuit. Depending on the output format
the flexible clock output is at either 148.5 MHz or 148.35 MHz. This clock is fed
back to the FPGA to drive the generator core functions, and sent to the FPGA
serializer clock inputs and the trigger o utput multiplexer.
The 54 M Hz input clock also registers the input frame pulse. After it is registered
at 54 MHz it needs to cross to the 148.5 MHz domain. For this to work
dete
rministically the phase of the two clocks is automatically controlled. The
status of this automatic control system is shown in the module diagnostic menu as
DDS1 phase.
Converter mode
In c
onverter mode, the fixed 148.5 MHz Ref clock is used as a training clock in
the input de-serializer. The FPGA then outputs a clock that was recovered from
the input. This clock is passed throu gh the jitter attenuator, to remove possible
jitter from the HD input, and then, like the generator mode clock, it drives the
serializer clocks and the trigger output multiplexer.
I
nput and output boards
The input board contains a cable equalizer to accommodate various cable lengths.
The equalizer output is sent to the FPGA. The input board also contains the trigger
output. The user can select the active pixel clock, or if in generator mode, a pulse
at either line o r field rate. The output is 50 Ω, to drive typical oscilloscope inputs.
The output board takes two channels from the FPGA serializers and buffers
them to drive 75 Ω cable. The output level is set by non-volatile electronic
potentiometers on the output board, so the calibration is captured in the board.
11–10 TG8000 Multiformat Test Signal Generator Service Manual
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