HD3G7 module theory of operation
HD3G7 module t
heory of operation
This section
describes the basic operation of the major circuit blocks in the
HD3G7 module. The discussions relate to the Block D iagram. (See Figure 11-1
on page 11-11.)
There is some circuitry on the HD3G7 Main circuit board which is not used.
Unused circuitry is not represented in the block diagram, nor is it discussed in
this theory of operation.
Overview
The HD3G7 module has three circuit boards: the main module board, which
mounts horizontally and contains the bulk of the circuitry, and two small input and
output boards. These input and output boards plug into the main board vertically
and prov
ide the rear BNC connections and the circuits required to buffer the
high-speed I/O signals.
The hea
rt of the HD3G7 generator is an FPGA, with other circuits that provide
support and ancillary functions. There are two basic operational modes: Generator
and Converter.
In generator mode the FPGA creates the output signal such as color bars or a
ramp. The information to create the signals is completely contained within the
FPGA. Serialization and scrambling is also done in the FPGA.
In converter mode an input signal a t 1.5 Gb/s HD rate is up-converted to 3 Gb/s.
De-serialization, up-conversion, and reserialization are all handled in the FPGA.
FPGA and associated circuits
A Programmable Logic Device (PLD) configures the FPGA by loading a file from
the Flash at power up. This configures the FPGA for normal operation; there is
a separate file for calibration.
The CPU interface connects to both the PLD and FPGA. During SW upgrade, the
Flash files are loaded from the mainframe via the PLD. The FPGA uses the CPU
connection to access the control registers.
Generator mode
In generator mode, the FPGA contains horizontal and vertical counters which
create the raster structure for the selected signal. These counters drive the FPGA
elements that create the actual video signals such as color bars or flat field, along
with the EAV and SAV info and the required CRCs. The video si gnals are then
scrambled, serialized, and sent at the full 3 Gb/s out of the FPGA to the output
boards.
TG8000 Multiformat Test Signal Generator Service Manual 11–9