Output:
Current DS
Steps removed: 0
Offset from Master: 0.000000000
Mean Path Delay: 0.000000000
Default DS
Number of Ports: 1
Two Step Clock: T
Priority 1: 128
Priority 2: 128
Domain: 0
Clock Identity: 12 34 56 FF FE 65 43 21
Clock Qual - Class: 248
Clock Qual - Accuracy: 254
Clock Qual - Variance: 0
Slave Only: F
Parent DS
Parent Stats: F
Parent Clock Identify: 12 34 56 FF FE 65 43 21
Parent Port Identify: 0
Parent Offset Var: 65535
Parent Phase Chnge Rate: 2147483647
GM Priority 1: 128
GM Priority 2: 128
GM Clck Qual - Class: 248
GM Clck Qual - Accuracy: 254
GM Clck Qual - Variance: 0
GM Clock Identify: 12 34 56 FF FE 65 43 21
Time Properties DS
Current UTC Offset: 0
Leap 59: F
Leap 61: F
Current UTC Offset Vald: T
PTP Timescale: T
Time Traceable: F
Frequency Traceable: F
Time Source: Internal Oscillator
Port DS
Clock Identify: 12 34 56 FF FE 65 43 21
Port Identify: 1
Port State: 6
Log Mn Delay Req Intrvl: 4
Peer mean Path Delay: 0
Log Announce Interval: 1
Announc Receipt Timeout: 3
Log Sync Interval: 0
Delay Mechanism: E2E
Log Mn PDelay Rq Intrvl: 0
Version Number: 2
Foreign Master DS 1
Announce Messages: 2
Frgn Mstr Clock Idntfy: 00 60 1A FF FE 01 54 29
Frgn Mstr Port Idntfy: 1