• Positive Transition Register (PTR) (.ptr): When a bit is set in this read-write register, it
enables a 0 to 1 change in the corresponding bit of the condition register to cause the
corresponding bit in the event register to be set.
An event is represented by a condition register bit changing from a 1 to 0 or 0 to 1. When an event
occurs and the appropriate NTR or PTR bit is set, the corresponding event register bit is set to 1. The
event bit remains latched to 1 until the event register is read or the status model is reset. When an
event register bit is set and its corresponding enable bit is set, the summary bit of the register is set
to 1. This, in turn, sets a bit in a higher-level condition register, potentially cascading to the associated
summary bit of the Status Byte Register.
Summary bit
The summary bit of each register is either set (1) or clear (0). A set summary bit indicates that one (or
more) of the enabled events in that register has occurred.
Queues
The Series 3700A uses queues to store messages. The queues include:
• Command queue: Holds commands that are available for execution.
• Output queue: Holds response messages.
• Error queue: Holds error and status messages.
When a queue contains data, it sets the condition bit for that queue in one of the registers. The
condition bits are:
• Command queue: CAV in the Operation Status Remote Summary Register
• Output queue: MAV in the Status Byte Register
• Error queue: EAV in the Status Byte Register
The CAV, MAV, and EAV bits in the registers are cleared when the queue is empty. Queues empty
when:
• Commands are executed
• Errors are read from the error queue
• Response messages are read from the instrument
All Series 3700A queues are first-in, first-out (FIFO).
The Status model diagrams shows how the queues are structured with the other registers.
Output queue
When the instrument is in the remote state, the output queue holds data that pertains to the normal
operation of the instrument. For example, when a print() command is sent, the response message
is placed in the output queue.
When data is placed in the output queue, the Message Available (MAV) bit in the status byte register
is set. A response message is cleared from the output queue when it is read. The output queue is
considered cleared when it is empty. An empty output queue clears the MAV bit in the status byte
register.
A message is read from the output queue by addressing the instrument to talk.
To Next Page
Loading...
Need help?
General
