Overview of Interrupts
M30240 Group
Rev.1.00 Sep 24, 2003 Page 340 of 360
4.1.4 Interrupt Sequence
An interrupt sequence is performed over a period from the instant an interrupt is accepted to the instant
the interrupt routine is executed.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the
execution of the instruction is completed, and transfers control to the interrupt sequence at the next
cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,
the processor temporarily suspends the instruction being executed, and transfers control to the interrupt
sequence.
In the interrupt sequence, the processor carries out the following:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading ad-
dress 00000
16
.
(2) Saves the content of the flag register (FLG) as it was immediately before the start of the interrupt
sequence in the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D Flag), and the stack pointer select flag (U
flag) to “0” (the U flag, however does not change if the INT instruction, in software interrupt numbers
32 through 63, is executed)
(4) Saves the content of the temporary register (Note) within the CPU in the stack area.
(5) Saves the content of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first
address of the interrupt routine.
Note: This register cannot be utilized by the user.
4.1.4.1 Saving Registers
In the interrupt sequence, only the contents of the flag register (FLG) and that of the program counter
(PC) are saved in the stack area.
First, the processor saves the 4 higher-order bits of the program counter, and the 4 upper-order bits
and 8 lower-order bits of the FLG register (16 bits in total) in the stack area. Afterward, it saves the 16
lower-order bits of the program counter. Figure 4.5 shows the state of the stack as it was before the
acceptance of the interrupt request, and the state of the stack after the acceptance of the interrupt re-
quest.
Save other necessary registers at the beginning of the interrupt routine using software. Using the
PUSHM instruction alone can save all the registers except the stack pointer (SP).
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