Programmable I/O Ports
M30240 Group
Rev.1.00 Sep 24, 2003 Page 110 of 360
1.2.26 Programmable I/O Ports
There are 63 programmable I/O ports: P0 to P3, P6 to P8 (excluding P8
5
), and P10. Each port can be
set independently for input or output using the direction register. A pull-up resistance for each block of
4 ports can be set. P8
5
is an input-only port and has no built-in pull-up resistance.
Figure 1.106, Figure 1.107 and Figure 1.108 show the programmable I/O ports.
Each pin functions as a programmable I/O port and as the I/O for the built-in peripheral devices.
To use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to
input mode. When the pins are used as the outputs for the built-in peripheral devices, they function as
outputs regardless of the contents of the direction registers. Unused I/O pins can be terminated as
shown in Figure 1.113 and Table 1.36 .
1.2.26.1 Direction registers
Figure 1.109 shows the direction registers.
These registers are used to choose the direction of the programmable I/O ports. Each bit in these reg-
isters corresponds one for one to each I/O pin.
Note: There is no direction register bit for P8
5
.
1.2.26.2 Port registers
Figure 1.110 shows the port registers.
These registers are used to write and read data for input and output to and from an external device.
A port register consists of a port latch to hold output data and a circuit to read the status of a pin. Each
bit in port registers corresponds one for one to each I/O pin.
1.2.26.3 Pull-up control registers
Figure 1.111 shows the pull-up control registers.The pull-up control register can be set to apply a pull-
up resistance to each block of 4 ports. When ports are set to have a pull-up resistance, the pull-up
resistance is connected only when the direction register is set for input.
1.2.26.4 High drive capacity registers
Figure 1.112 shows the Port 2 and PWM drive capacity register. Port 2 can be configured to drive an
LED by increasing the drive strength of the corresponding bit’s N-channel transistor. Each Timer out-
put (TA0
OUT
toTA4
OUT
) can be configured for high-drive capability by increasing the drive strength of
the corresponding bits.
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