RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1420
Dec 10, 2015
(4) When transmit completes successfully, the CFMC[5:0] value is cleared to H'00. Setting the CFIM bit to 1 (a FIFO
transmit interrupt request is generated each time a message has been transmitted) sets the CFTXIF flag in the
CFSTSk register to 1 (a transmit/receive FIFO transmit interrupt request is present). The CFTXIF flag can be
cleared by the program.
(5) If another CAN node on the CAN bus is transmitting data (not from transmit/receive FIFO buffer k), transmit/receive
FIFO buffer k cannot be disabled immediately even if the CFE bit in the CFCCLk register is cleared to 0 (no
transmit/receive FIFO buffer k is used) during transmit priority determination. (The CFEMP flag in the CFSTSk
register is not set to 1 (the transmit/receive FIFO buffer contains no message (buffer empty)) immediately.)
(6) After the internal processing time has passed, transmit/receive FIFO buffers are disabled and the CFMC[5:0] bits in
the CFSTSk register are cleared to H'00 and the CFEMP flag is set to 1. When the transmit/receive FIFO buffer k is
not transmitting data and is not selected as the next transmit buffer and priority determination is not in progress, the
transmit/receive FIFO buffer k is immediately disabled. (The CFMC[5:0] bits are cleared to H'00 and the CFEMP flag
is set to 1.)
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