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See Also Transparent Encoding Applications and Support Overview on page 12•

• Using Phase-Correction FIFO Buffer with Transparent Encoding on page 14

• Using Send Timing (ST) Clocking for Higher Speed Circuits with Transparent Encoding

on page 16

• Configuring Transparent Encoding for CTP Bundles (CTP Menu) on page 60

• Configuring Transparent Encoding for CTP Bundles (CTPView) on page 58

Using Phase-Correction FIFO Buffer with Transparent Encoding

The transparent encoding feature provides a phase-correction FIFO buffer. This FIFO

buffer aligns the clock and data phase relationship on a transparent encoded circuit in

which the clock travels in one direction through the network, and the data travels in the

opposite direction. The transparent FIFO buffer is needed because of the latency of signal

transport over the IP network.

Figure 4 on page 14 shows the phase-correction FIFO buffers. You can enable the

phase-correction FIFO buffer at either end of the circuit. You would not enable the FIFO

buffer at both ends of the circuit.

Figure 4: Transparent Encoding with Phase-Correction FIFO Buffers

Transparent Circuit

DTE DCE

g015406

CTS

DSR

RTS

DTR

RTS

DTR

CTS

DSR

Pin Pin

FIFO FIFO

Figure 5 on page 15 shows the paths of the clock and data through the phase-correction

FIFO buffer that is enabled on the transparent circuit on the right.

•

The clock enters the network from the DCE, goes to the DTE, and then clocks data into

the network on the DTE. The clock is also looped back on the DTE to enter the network

in phase with the data as it travels from the DTE to the DCE.

•

The data enters the FIFO buffer in phase with the clock passing through the network

from the DTE to the DCE, while data is clocked out of the FIFO buffer with the clock

that entered the network from the DCE, which is in phase with the user clock.

Using Bundles to Create Logical Configurations for Physical Interfaces, CTP Release 7.3, CTPView Release 7.3

Juniper CTP Series User Manual

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