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3.21.3 Precautions
This section describes precautions for executing the high-speed interrupt function.
(1) Functions that delay the startup of high-speed interrupts
When any of the functions in the table below is being executed, high-speed interrupts cannot be executed at
preset intervals.
Item Operation when executed
Multiple CPU system configuration The startup of a high-speed interrupt delays for about 15µs.
Connection of the QA1S5B, QA1S6B, and QA6B
The startup of a high-speed interrupt delays for about 18µs for the first level and delays
for about 30µs for the second and later levels.
Interrupt program (I0 to I48, I50 to I255), fixed scan execution type
program
Only one interrupt is executed at a time. A high-speed interrupt starts after the execution
of an interrupt program or fixed scan execution type program ends.
Operation when a continuation error occurs
The startup of a high-speed interrupt delays for the time required to detect a continuation
error (instruction execution time + continuation error notification time (20µs)).
Execution of an instruction
Interrupts are disabled while an instruction is being executed. A high-speed interrupt
starts after the execution of the instruction is completed.
Link direct device, instruction that accesses to module access
device, MC protocol, and device test
The startup of a high-speed interrupt delays for more than 15µs.
I/O refresh, link refresh, auto refresh (intelligent function module),
and multiple CPU auto refresh
The startup of a high-speed interrupt delays for the following period of time.
• When I/O refresh is performed on the module mounted
• on the main base unit: 24µs maximum
• on the extension base unit: 40µs maximum
• When link refresh or auto refresh is performed on the module mounted
• on the main base unit: 30µs maximum
• on the extension base unit: 70µs maximum
• When multiple CPU auto refresh is performed on the module mounted
• on the main base unit: 250µs maximum
Interlink transfer
The startup of a high-speed interrupt delays for the following period of time.
• Interlink transfer on the main base unit: 15µs maximum
• Interlink transfer on the extension base unit: 30µs maximum
Ladder monitor, device batch monitor, and entry data monitor
The startup of a high-speed interrupt delays for the monitoring time (0.121µs x number of
device points + 9µs). If self-monitoring and monitoring via any intelligent function module
are requested at the same time, the startup of a high-speed interrupt delays for about
70µs.
Local device monitor
The startup of a high-speed interrupt delays for the monitoring time (340µs + performance
when the local devices are used).
Buffer memory batch monitor
The startup of a high-speed interrupt delays for about 820µs. (The number of points to be
monitored: 55)
Monitor condition setting
The startup of a high-speed interrupt delays for the following period of time.
• When step is specified: 30µs
• When internal user device is specified: 15µs
Read from PLC (during RUN)
The startup of a high-speed interrupt delays for the following period of time.
• Reading data from the device memory (59K words): 250µs
• Reading data from other memory: 15µs
Write to PLC (during RUN), file transfer function (FTP)
The startup of a high-speed interrupt delays for the following period of time.
• Writing data to the comment file in the program memory or standard RAM: 60µs or
longer
• Writing data to the file register in the standard RAM: 60µs or longer
• Writing data to other memory: 15µs
Forced disablement of SD memory card The startup of a high-speed interrupt delays for about 20µs.
Program memory batch download The startup of a high-speed interrupt delays for about 15µs.
Executional conditioned device test
The startup of a high-speed interrupt delays for the following period of time.
• When registered/disabled: 50µs maximum
• During execution: Tested using the same program name and step No.
• Internal user device: 12µs × (number of device points) + 25µs
• I/O device: 28µs × (number of device points) + 25µs
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