5 I/O Memory
5-2
CP2E CPU Unit Software User’s Manual(W614)
5-1 Overview of I/O Memory Areas
This section describes the I/O memory areas in a CP2E CPU Unit.
Data can be read and written to I/O memory from the ladder programs. I/O memory consists of an area
for I/O with external devices, user areas, and system areas.
In the CIO Area, input bit addresses range from CIO 0 to CIO 99, output bit addresses range from CIO
100 to CIO 199 and addresses for serial PLC links range from CIO 200 to CIO 289.
The bits and words in the CIO Area are allocated to built-in I/O terminals on the CP2E CPU Unit and to
the Expansion Units and Expansion I/O Units.
Input words and output bits that are not allocated may be used as work bits in programming.
Refer to 5-2 I/O Bits
5-1-1 I/O Memory Areas
CIO Area (CIO 0 to CIO 289)
Input bits (starting from CIO 0)
User Areas
Holding Area (H)
DM Area (D)
Timer Area (T)
Counter Area (C)
Index Registers (IR)
Data Registers (DR)
Output bits (starting from CIO 100)
Work Area (W)
System Areas
Auxiliary Area
(A)
Condition Flags
Clock Pulses
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