RL78/F13, F14 CHAPTER 2 PIN FUNCTIONS
R01UH0368EJ0210 Rev.2.10 78
Dec 10, 2015
2.2.11 P120 to P127 (Port 12)
The 100-pin products of RL78/F14 has P120 and P125 to P127 I/O port pins, and the 80-pin products of RL78/F13 (CAN
and LIN incorporated) has P120, P125, and P126 I/O port pins. P121 to P124 are input port pins and provided in both
products. These pins also function as A/D converter analog input, external interrupt request input, resonator connection for
the main system clock, resonator connection for the subsystem clock, external clock input for the main system clock, external
clock input for the subsystem clock, serial interface slave select input, serial interface data output, timer I/O, and SNOOZE
status output.
Only for the P120 and P125 to P127 pins, use of an on-chip pull-up resistor can be specified by pull-up resistor option
register 12 (PU12).
For input to the P125 pin, a CMOS input buffer or a TTL input buffer can be selected using the port input mode register
12 (PIM12).
For output from the P120 pin, CMOS output or N-ch open-drain output can be selected using the port output mode register
12 (POM12).
For the P125 pin, the input threshold level can be specified using the port input threshold control register 12 (PITHL12).
Input to the P120 and P125 pins can be specified as digital I/O or analog input in 1-bit units, using port mode control
register 12 (PMC12).
The following operation modes can be specified in 1-bit units.
(1) Port mode
P120 and P125 to P127 function as I/O port pins. These pins can be set to input or output port using port mode register
12 (PM12).
P121 to P124 function as input port pins.
(2) Control mode
P120 to P127 function as A/D converter analog input, external interrupt request input, resonator connection for the main
system clock, resonator connection for the subsystem clock, external clock input for the main system clock, external clock
input for the subsystem clock, serial interface slave select input, serial interface data output, timer I/O, and SNOOZE status
output.
(a) ANI24, ANI25
These are analog input pins of the A/D converter. For details, see 12.10 (5) Analog input (ANIn) pins.
(b) INTP1, INTP4
These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and
falling edges) can be specified.
(c) X1, X2
These are resonator connection pins for the main system clock.
(d) EXCLK
This is an external clock input pin for the main system clock.
(e) XT1, XT2
These are resonator connection pins for the subsystem clock.
(f) EXCLKS
This is an external clock input pin for the subsystem clock.
(g) SSI01
This is a slave select input pin of the CSI01 (SPI01) serial interface.
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