RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 600
Dec 10, 2015
8.2.18 Timer RD Counter i (TRDi) (i = 0 or 1)
[Timer Mode]
Access the TRDi register in 16-bit units. Do not access it in 8-bit units.
[Reset Synchronous PWM Mode and PWM3 Mode]
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units. The TRD1 register is not used in reset synchronous
PWM mode and PWM3 mode.
[Complementary PWM Mode (TRD0)]
Access the TRD0 register in 16-bit units. Do not access it in 8-bit units.
[Complementary PWM Mode (TRD1)]
Access the TRD1 register in 16-bit units. Do not access it in 8-bit units.
Figure 8-29. Format of Timer RD Counter i (TRDi) (i = 0 or 1) [Timer Mode]
Address: F0276H (TRD0), F0286H (TRD1) After Reset: 0000H
Note
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDi
— — — — — — — — — — — — — — — —
— Function Setting Range R/W
Bits 15 to 0 Count the count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSRi register is set to 1.
0000H to FFFFH R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN =
0 in the PER1 register. If it is necessary to read the initial value, set f
CLK to fIH and TRD0EN = 1 before reading.
Figure 8-30. Format of Timer RD Counter i (TRDi) (i = 0 or 1) [Reset Synchronous PWM Mode and PWM3 Mode]
Address: F0276H (TRD0), F0286H (TRD1) After Reset: 0000H
Note
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDi
— — — — — — — — — — — — — — — —
— Function Setting Range R/W
Bits 15 to 0 Count the count source. Count operation is incremented.
When an overflow occurs, the OVF bit in the TRDSR0 register is set to 1.
0000H to FFFFH R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN =
0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN = 1 before reading.
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