RL78/F13, F14 CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
R01UH0368EJ0210 Rev.2.10 692
Dec 10, 2015
10.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0).
10.4.1 Operation as output pin
The PCLBUZ0 pin is output as the following procedures.
<1> Set the bit in the port mode register 14 (PM14) and the bit in the port register 14 (P14) corresponding to the port
used as a PCLBUZ0 pin.
<2> Clear the output latches of PM140 and P140 to 0.
<3> Select the output clock with bits 0 to 3 (CCS00 to CCS02, CSEL0) of the clock output select register 0 (CKS0) of
the PCLBUZ0 pin (output in disabled status).
<4> Set bit 7 (PCLOE0) of the CKS0 register to 1 to enable clock/buzzer output.
Remark The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or
disabling clock output (PCLOE0 bit) is switched. At this time, pulses with a narrow width are not output.
Figure 10-5 shows enabling or stopping output using the PCLOE0 bit and the timing of outputting the clock.
Figure 10-5. Remote Control Output Application Example
10.5 Notes on Clock Output/Buzzer Output Controller
When the CPU enters STOP mode within 1.5 clock cycles of main system clock after the setting to disable output is made
(PCLOE0 = 0) while the main system clock is selected for PCLBUZ0 output (CSEL0 = 0), the pulse width of the PCLBUZ0
output is narrowed.
PCLOE0
1 clock elapsed
Narrow pulses are not recognized
Clock output
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