Renesas RL78/F13 User Manual

RL78/F13, F14 CHAPTER 21 INTERRUPT FUNCTIONS
R01UH0368EJ0210 Rev.2.10 1514
Dec 10, 2015
21.4.5 Interrupt request hold
There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed below.
 MOV PSW, #byte
 MOV PSW, A
 MOV1 PSW. bit, CY
 SET1 PSW. bit
 CLR1 PSW. bit
 RETB
 RETI
 POP PSW
 BTCLR PSW. bit, $addr20
 EI
 DI
 SKC
 SKNC
 SKZ
 SKNZ
 SKH
 SKNH
 MULHU
 MULH
 MACHU
 MACH
 Manipulation instructions for the IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H,
MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H,
and PR13L registers
Caution The BRK instruction is not one of the above-listed interrupt request hold instructions. However, the
software interrupt activated by executing the BRK instruction causes the IE flag to be cleared.
Therefore, even if a maskable interrupt request is generated during execution of the BRK instruction,
the interrupt request is not acknowledged.
Figure 21-16 shows the timing at which interrupt requests are held pending.
Figure 21-16. Interrupt Request Hold
Remarks 1. Instruction N: Interrupt request hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
Instruction N Instruction M
PSW and PC saved, jump
to interrupt servicing
Interrupt servicing
program
CPU processing
××IF
<R>

Renesas RL78/F13 Specifications

General

CPU Core	RL78
Architecture	16-bit
Maximum Clock Frequency	32 MHz
ADC	10-bit
Package	LQFP, QFN
Operating Temperature	-40°C to +85°C
Operating Voltage	1.8 V to 5.5 V
Communication Interfaces	UART, I2C, SPI