RL78/F13, F14 CHAPTER 19 DTC
R01UH0368EJ0210 Rev.2.10 1449
Dec 10, 2015
19.3 Operation
When the DTC is activated, control data is read from the DTC control data area to perform data transfers and control
data after data transfer is written back to the DTC control data area. Twenty-four sets of control data can be stored in the
DTC control data area, which allows 24 types of data transfers to be performed.
There are two transfer modes (normal mode and repeat mode) and two transfer sizes (8-bit transfer and 16-bit transfer).
When the CHNE bit in the DTCCRj (j = 0 to 23) register is set to 1 (chain transfers enabled), multiple control data is read
and data transfers are continuously performed by one activation source (chain transfers).
A transfer source address is specified by the 16-bit register DTSARj, and a transfer destination address is specified by
the 16-bit register DTDARj.
The values in registers DTSARj and DTDARj are separately incremented or fixed according to the control data after the
data transfer.
This product supports high-speed transfer operation. The high-speed transfer can be realized by allocating the dedicated
control data to the SFR area instead of the RAM area. To perform basic operation, normal mode requires five clock cycles
to read vector and control data, while high-speed transfer requires one cycle. In addition, to write back control data, normal
mode requires a maximum of three clock cycles, while high-speed transfer requires one cycle.
19.3.1 Activation Sources
The DTC is activated by an interrupt signal from the peripheral functions. The interrupt signals to activate the DTC are
selected with the DTCENi (i = 0 to 5
Note 2
) register.
The DTC sets the corresponding bit among bits DTCENi0 to DTCENi7 in the DTCENi register to 0 (activation disabled)
during operation when the setting of data transfer (the first transfer in chain transfers) is either of the following:
- A transfer that causes the DTCCTj (j = 0 to 23) register value to change to 0 in normal mode
- A transfer that causes the DTCCTj register value to change to 0 while the RPTINT bit in the DTCCRj register is 1
(interrupt generation enabled) in repeat mode
Figure 19-20 shows the DTC internal operation flowchart.
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