RL78/F13, F14 CHAPTER 13 D/A CONVERTER (RL78/F14 Only)
R01UH0368EJ0210 Rev.2.10 774
Dec 10, 2015
13.4.2 Operation in Real-Time Output Mode
D/A conversion is performed on each channel using the individual interrupt request signals from the ELC as triggers.
The setting method is described below.
<1> Set the DACEN bit of the peripheral enable register 1 (PER1) to 1 to start the supply of the input clock to the
D/A converter.
<2> Use the port configuration register (ADPC) to set the ports to analog pins.
<3> Set the ANO0EN bit of the D/A converter mode register 2 (DAM2) to 1 (analog output enable). When setting
bits 5 and 4 (CVRS1 and CVRS0) in the comparator I/O select register (CMPSEL) to 10B (internal reference
voltage (DAC output) is selected), set the ANO0EN bit in this register to 0 (analog output is disabled).
<4> Set the DAMD0 bit of the D/A converter mode register (DAM) to 0 (normal mode).
<5> Set the analog voltage value to be output to the ANO0 pin to the D/A conversion value setting register 0
(DACS0).
<6> Set the DACE0 bit of the DAM register to 1 (D/A conversion enable).
D/A conversion starts, and then, after the settling time elapses, the analog voltage set in step <5> is output to
the ANO0 pin.
<7> Use the event output destination select register (ELSELRn) to set the real-time trigger signal.
<8> Set the DAMD0 bit of the DAM register to 1 (real-time output mode).
<9> Start the operation of the ECL request source.
Steps <1> to <9> above constitute the initial settings.
<10> Generation of the real-time output triggers starts D/A conversion and the analog voltage set in step <5> will
be output to the ANO0 pin after a settling time has elapsed.
Set the analog voltage value to be output to the ANO0 pin, to the DACS0 register before performing the next D/A
conversion (real-time output trigger is generated).
When the DACE0 bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops.
If the ports are set to digital pins by using the ADPC register, the ANO0 pin goes into a high-impedance state when the
PM80 bit of the PM8 register for the port = 1 (input mode), and the ANO0 pin outputs the set value of the P8 register when
the PM80 bit = 0 (output mode).
Cautions 1. Even if 1, 0, and then 1 is set to the DACE0 bit, there is a wait after 1 is set for the last time.
2. Make the interval between each generation of the ELC event request trigger signal longer than the
settling time. If an ELC event request trigger signal is generated during the settling time, D/A
conversion is aborted and reconversion starts.
3. Even if the generation of the ELC event request trigger signal and rewriting of the DACS0 register
conflict, the correct D/A conversion result is output.
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