RL78/F13, F14 CHAPTER 23 STANDBY FUNCTION
R01UH0368EJ0210 Rev.2.10 1519
Dec 10, 2015
Cautions 1. The STOP mode can be used only when the CPU is operating on the main system clock. The
STOP mode cannot be set while the CPU operates with the PLL clock or the subsystem/low-
speed on-chip oscillator select clock. The HALT mode can be used when the CPU is operating
on either the main system clock or the subsystem/low-speed on-chip oscillator select clock.
2. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating
with main system clock before executing STOP instruction (except for the setting unit of
SNOOZE mode).
3. When using the A/D converter and the LIN/UART module in the SNOOZE mode, set up the A/D
converter mode register 2 (ADM2) and the UART standby control register (LUSCn) before
switching to the STOP mode. For details, see 17.2 Register Descriptions.
4. The following sequence is recommended for operating current reduction of the A/D converter when
the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of A/D converter mode
register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the STOP instruction.
5. It can be selected by the option byte whether the WDT-dedicated low-speed on-chip oscillator
continues oscillating or stops in the HALT or STOP mode. For details, see CHAPTER 29 OPTION
BYTE.
23.2 Registers controlling standby function
Oscillation stabilization time when this LSI is released from the STOP mode is controlled by the following two registers.
ï‚· Oscillation stabilization time counter status register (OSTC)
ï‚· Oscillation stabilization time select register (OSTS)
Output from the port when a source condition for release from the STOP mode is generated is inverted by the following
register.
ï‚· STOP status output control register (STPSTC)
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
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