RL78/F13, F14 CHAPTER 36 ELECTRICAL SPECIFICATIONS (GRADE Y)
R01UH0368EJ0210 Rev.2.10 1793
Dec 10, 2015
(T
A = -40 to +150C, 2.7 V EVDD0 = EVDD1 = VDD 5.5 V, VSS = EVSS0 = EVSS1 = 0 V) (2/2)
Items Symbol Conditions MIN. TYP. MAX. Unit
Input leakage
current, high
I
LIH1
P00 to P03, P10 to P17,
P30 to P32, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P92 to
P97
Note
, P106, P107,
P120, P125 to P127,
P140, P150 to P157
V
I = EVDD0 1 A
ILIH2
P33, P34, P80 to P87,
P90 to P97
Note
, P100 to
P105, P137, RESET
V
I = VDD 1 A
ILIH3 P121 to P124
(X1, X2, EXCLK,
EXCLKS)
V
I = VDD
In input port or
external clock
input
1 A
In resonator
connection
10 A
Input leakage
current, low
I
LIL1
P00 to P03, P10 to P17,
P30 to P32, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P92 to
P97
Note
, P106, P107,
P120, P125 to P127,
P140, P150 to P157
V
I = EVSS0 -1 A
ILIL2
P33, P34, P80 to P87,
P90 to P97
Note
, P100 to
P105, P137, RESET
V
I = VSS -1 A
ILIL3 P121 to P124
(X1, X2, EXCLK,
EXCLKS)
V
I = VSS
In input port or
external clock
input
-1 A
In resonator
connection
-10 A
On-chip pull-up
resistance
R
U
P00 to P03, P10 to P17,
P30 to P32, P40 to P47,
P50 to P57, P60 to P67,
P70 to P77, P92 to P97,
P100 to P107, P120,
P125 to P127, P140,
P150 to P157
V
I = EVSS0, in input port
10 20 100 k
Note For pin I/O buffer power supplies, refer to Table 4-1 Pin I/O Buffer Power Supplies.
Caution P10 to P17, P60 to P63, P70 to P72, and P120 do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins.
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