RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 410
Dec 10, 2015
(3) Change the CPU from operating with the high-speed on-chip oscillator clock (B) or operating with the high-
speed system clock (C) to operating with the subsystem clock (D).
Set the RTCLPC bit of the OSMC register.
Set the SELLOSC bit of the CKSEL register to 0.
Set the CMC register (EXCLKS = x, OSCSELS = 1, AMPHS[1:0] = xx).
Note
Set the XTSTOP bit of the CSC register to 0.
Wait for oscillation stabilization.
Set the CSS bit of the CKC register to 1.
Confirm that the CLS bit of the CKC register is set to 1.
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
(4) Change the CPU from operating with the high-speed on-chip oscillator clock (B) or operating with the high-
speed system clock (C) to operating with the low-speed on-chip oscillator clock (M).
Set the SELLOSC bit of the CKSEL register to 1.
Set the CMC register (EXCLKS = x, OSCSELS = 1).
Note
Set the CSS bit of the CKC register to 1.
Confirm that the CLS bit of the CKC register is set to 1.
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
(5) Change the CPU from operating with the high-speed on-chip oscillator clock (B) or operating with the high-
speed system clock (C) to operating with the PLL clock (K).
Set the PLLCTL register (PLLDIV1 = x, LCKSEL[1:0] = xx, PLLDIV0 = x, PLLMUL = x).
Wait for the selection of the PLL multiplication value to become effective (After setting the PLLMUL bit, wait for at
least 1 s).
Set the PLLON bit of the PLLCTL register to 1.
Confirm that the LOCK bit of the PLLSTS register is set to 1 (checking PLL locked state).
Set the MDIV [2:0] bits of the MDIV register.
Set the SELPLL bit of the PLLCTL register to 1.
Confirm that the SELPLLS bit of the PLLSTS register is set to 1.
(6) Change the CPU from operating with the high-speed system clock (C) to operating with the high-speed on-chip
oscillator clock (B).
Set the HIOSTOP bit of the CSC register to 0.
Note
Set the MCM0 bit of the CKC register to 0.
Confirm that the MCS bit of the CKC register is set to 0.
Note When oscillation starts from a high-speed on-chip oscillator clock stop state (HIOSTOP = 1), have the software
wait for the following oscillation accuracy stabilization time, and then change the clock.
FRQSEL4 of the user option byte (000C2H/020C2H) = 0: 18 s to 65 s
FRQSEL4 of the user option byte (000C2H/020C2H) = 1: 18 s to 105 s
To Next Page
Loading...
Need help?
General
