RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 643
Dec 10, 2015
Figure 8-59. Operation Example in Complementary PWM Mode
m
n
m + 2 - p
p
p
0000H
m + 1
n + 1
n + 1 - p p n + 1 - p
n
n
m
-
p
-
n + 1
n
Count source
Bits TSTART0 and TSTART1
in TRDSTR register
TRDIOB0 output
Initial output is high
Active level is low
Initial output is high
Remark
CMD0, CMD1: Bits in TRDFCR register
i = 0 or 1
m: Value set in TRDGRA0 register
n: Value set in TRDGRB0 register
p: Value set in TRD0 register
The above diagram applies under the following condition :
Bits OLS1 and OLS0 in TRDFCR are set to 0 (initial output level is high, active level is low for normal-phase and counter-phase).
Transfer (when bits CMD1 and CMD0 are set to 11B)
Transfer (when bits CMD1 and CMD0
are set to 10B)
Set to 0 by a program
Set to 0 by a program
Modify with a program
Following data
Set to 0 by a program
(n + 1 - p) × 2
Width of counter-phase active level
Time
Value in TRD1 register
Value in TRD0 register
Set to
FFFFH
Dead
time
(m-p-n+1) × 2
Width of normalphase
active level
TRDIOD0 output
TRDIOC0 output
UDF bit in
TRDSR1 register
IMFA bit in
TRDSR0 register
TRDGRB0 register
TRDGRD0 register
IMFB bit in
TRDSR0 register
Value in TRDi register
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