GE Power Management
489 Generator Management Relay 6-3
6 COMMUNICATIONS 6.1 ELECTRICAL INTERFACE
6
6.1.5 CRC-16 ALGORITHM
Once the following algorithm is complete, the working register "A" will contain the CRC value to be transmitted. Note that
this algorithm requires the characteristic polynomial to be reverse bit ordered. The MSbit of the characteristic polynomial is
dropped since it does not affect the value of the remainder. The following symbols are used in the algorithm:
Symbols: --> data transfer
A 16 bit working register
A
low
low order byte of A
A
high
high order byte of A
CRC 16 bit CRC-16 result
i, j loop counters
(+) logical EXCLUSIVE-OR operator
N total number of data bytes
D
i
i-th data byte (i = 0 to N-1)
G 16 bit characteristic polynomial = 1010000000000001 (binary) with MSbit dropped and bit order reversed
shr (x) right shift operator (the LSbit of x is shifted into a carry flag, a '0' is shifted into the MSbit of x, all other bits
are shifted right one location)
Algorithm:
1. FFFF (hex) --> A
2. 0 --> i
3. 0 --> j
4. D
i
(+) A
low
--> A
low
5. j + 1 --> j
6. shr (A)
7. Is there a carry? No: go to step 8.
Yes: G (+) A --> A and continue.
8. Is j = 8? No: go to 5.
Yes: continue.
9. i + 1 --> i
10. Is i = N? No: go to 3.
Yes: continue.
11. A --> CRC
6.1.6 TIMING
Data packet synchronization is maintained by timing constraints. The receiving device must measure the time between the
reception of characters. If three and one half character times elapse without a new character or completion of the packet,
then the communication link must be reset (i.e. all slaves start listening for a new transmission from the master). Thus at
9600 baud a delay of greater than 3.5 × 1 / 9600 × 10 = 3.65 ms will cause the communication link to be reset.
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