The output of the 9914 IC is in standard IEEE-488 format; the
eight data lines (DlOl-DI08), the three handshake lines
(DAV, NRFD, NDAC), and the five management lines
(ATN, REN, IFC, SRQ, and EOI) are all active low with ap-
proximately zero volts representing a logic one. The two
IEEE-488 bus drivers, U119 and U120, are necessary to bring
the drive capability of the interface up to the requirements of
the IEEE-488 standard, which included provisions for up to 15
devices to be connected to the bus at one time. The outputs of
the bus drivers are connected to JlOlO, which is a standard
IEEE-488 connector.
6.6.6 Input/Output Circuitry
Additional MPU functions include the control of the Meter
Complete and External Trigger Input, analog-to-digital con-
verter control, and voltage source control.
At the end of its conversion cycle, the Model 617 sends a
pulse out the Meter Complete jack on the rear panel. This
function is performed by the PB2 line of the MPU through
U102A configured as a buffer/inverter. Diodes CR104 and
CR105 and resistor RlO2 protect the circuit output.
UlOZD, UlO5B. and associated components process the in-
coming trigger signal. U102D buffers and inverts the signal,
while U105B latches the trigger pulse. The pulse is then read
by the MPU through PA6. PBl is used to reset the trigger
latch once the pulse is read. Note that PB1 is also used to read
the status of the calibration jumper (WlOl) during the calibra-
tion program.
As with the Meter Complete output, protection of the Exter-
nal Trigger input is necessary to protect the device from over-
voltage inputs. External Trigger protection components in-
clude R101, CR102, and CR103.
A/D control information is fed out the PB3 and PB5 ter-
minals through U102B. A pulse width modulation scheme is
used with 18 and 50~s~ pulses representing logic 0 and logic 1
respectively. A 2Oi$sec pulse is used to strobe data into the
A/D and serial-parallel control circuits. Note that this infor-
mation is used to control the A/D converter as well as to con-
trol the input preamplifier (through relays), set the ranging
amplifier gain, and to control the three phases of the measure-
ment cycle. Isolation is provided by opto-isolator Ul22.
Because of this isolation scheme, input signal common can be
floated up to &SOOV above chassis ground while digital com-
mon remains within C3OV of ground.
In a similar fashion, A/D data is routed in from the A/D con-
verter through opto-isolator U121. The MPU reads this data
through the TIMER terminal. As data pulses come in, an in-
ternal a-bit timer is incremented until 256 counts have occur-
red. When all counts have been taken, an internal interrupt is
generated, which causes to MPU to read the timer data. A
separate software counter is then decremented, and the pro-
cess repeats. Because of this data input scheme, MPU time
necessary to read the A/D converter data is minimized, and
the processor can concentrate on other important tasks.
The voltage source is controlled in a manner similar to that
used to control the A/D converter. Control information is
transmitted out the PB3 and PB4 terminals of the MPU
through U102C. Once again, a pulse width modulation
scheme is used to transmit the 12 bit data necessary to control
the DAC in the voltage source section. 1COV isolation is af-
forded by opto-isolator U124 located in the voltage source
section.
Data transmission is controlled by a 81.92kI-I~ clock. This
clock is generated by U103 by dividing down the 655.36kHz
system clock. The clock signal is transmitted through R105D
through isolator U123, which is located in the voltage source
section.
Voltage source overload data is fed in through opto-isolator
U125 to the PA7 terminal of the MPU. When the 2mA cur-
rent limit of the voltage source is exceeded, PA7 goes high.
The necessary software routine is used to flash the OPERATE
LED, indicating to the operator that an overload has occur-
red.
6.6.6 Display Circuitry
Display circuitry includes those elements necessary to control
the seven and 14 segment readouts, the front panel annun-
ciator LEDs, and to read the front panel switches. The display
circuitry schematic may be found on drawing number
617-116 located at the end of Section 8.
The display circuitry consists of the LED readouts (DSZOl-
DS206). the LED annunciators (DS207-DS224), the segment
drivers (U201 and U202). and the digit select circuitry (U204,
U201, and U203). DS202-DS205 are standard 7-segment
units, while DS206 is a dual 1Csegment display.
The display is updated at 1.56msec intervals. Timing for this
process is performed by a 64OHz clock which controls the seg-
ment latches, UllO and U116, located on the mother board.
Each time an interrupt is generated, the MPU writes segment
data for two digits to the segment latches. The two latches
outputs are then enabled in sequence by the 640Hz clock.
6-12
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