Rigol DS1000Z Series User Manual

RIGOL Chapter 7 Protocol Decoding
DS1000Z User’s Guide
7-2
Parallel Decoding
Parallel bus consists of clock line and data line. As shown in the figure below, CLK is
the clock line, while Bit0 and Bit1 are the 0 bit and 1st bit on the data line
respectively.
Bit0
Bit1
CLK
The oscilloscope will sample the channel data on the rising edge, falling edge or the
rising&falling edges of the clock and judge each data point (logic “1” or logic “0”)
according to the preset threshold level.
Press MATH  Decode1  Decoder to select “Parallel” and open the parallel
decoding function menu.
1. Press Decode to turn on or off the decoding function.
2. Clock Line Setting (CLK)
Press CLK to select any channel (CH1-CH4) as the clock channel. If “OFF” is
selected, no clock channel is set.
Press Edge to set the oscilloscope to sample the channel data on the rising edge
(
), falling edge ( ) or rising&falling edges ( ). If no clock channel is
selected, the instrument will sample when the channel data jumps in the
decoding.
3. Data Line Setting
 Set the bus bits
Press Width to set the data width of the parallel bus namely the number of
bits per frame. The default is 1 and the maximum is 16 bits (Bit0,
Bit1…Bit15).
 Specify data channel for each bit.
First, press Bit X to select the bit that needs to specify channel. The default

Rigol DS1000Z Series Specifications

General

Brand	Rigol
Model	DS1000Z Series
Category	Test Equipment
Language	English