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1 CHAPTER OVERVIEW

The P141, P142, P143, P144, P145 provides a wide range of current protection functions. This chapter describes the

operation of these functions including the principles, logic diagrams and applications.

This chapter contains the following sections:

Chapter O

verview 87

Overcurrent Protection Principles 88

Phase Overcurrent Protection 98

Voltage Dependent Overcurrent Element 105

Current Setting Threshold Selection 109

Cold Load Pickup 110

Selective Logic 113

Timer Setting Selection 115

Negative Sequence Overcurrent Protection 116

Earth Fault Protection 120

Sensitive Earth Fault Protection 130

Thermal Overload Protection 139

Broken Conductor Protection 144

Blocked Overcurrent Protection 146

Second Harmonic Blocking 149

Load Blinders 152

Neutral Admittance Protection 156

Busbar Protection 159

P14x Chapter 6 - Current Protection Functions

P14xEd1-TM-EN-1 87

Default Chapter3
- Table of Contents3
Chapter 1 Introduction27
- Rear Serial Port28
Chapter Overview29
- Trip Circuit Supervision Scheme29
- Cip29
Foreword30
- Target Audience30
- Typographical Conventions30
- Cip30
- Nomenclature31
- Cip31
Product Scope32
- Ordering Options32
- Cip32
Features and Functions33
- Protection Functions33
- Control Functions34
- Measurement Functions34
- Communication Functions34
Compliance36
Functional Overview37
- Figure 1: Functional Overview37
Chapter 2 Safety Information39
Chapter Overview41
Health and Safety42
Symbols43
Installation, Commissioning and Servicing44
- Lifting Hazards44
- Electrical Hazards44
- UL/CSA/CUL Requirements45
- Fusing Requirements45
- Equipment Connections46
- Protection Class 1 Equipment Requirements46
- Pre-Energisation Checklist47
- Peripheral Circuitry47
- Upgrading/Servicing48
Decommissioning and Disposal49
Regulatory Compliance50
- EMC Compliance: 2014/30/EU50
- LVD Compliance: 2014/35/EU50
- R&TTE Compliance: 2014/53/EU50
- UL/CUL Compliance50
- ATEX Compliance: 2014/34/EU50
Chapter 3 Hardware Design53
Chapter Overview55
Hardware Architecture56
- Figure 2: Hardware Architecture56
Mechanical Implementation57
- Housing Variants57
- Figure 3: Exploded View of IED57
- List of Boards58
Front Panel59
- Front Panel Compartments59
- Figure 4: Front Panel (60TE)59
- HMI Panel60
- Front Serial Port (SK1)60
- Figure 5: HMI Panel60
- Front Parallel Port (SK2)61
- Fixed Function Leds61
- Function Keys61
- Programable Leds62
Rear Panel63
- Figure 6: Rear View of Populated Case63
- Figure 7: Terminal Block Types64
Boards and Modules65
- Pcbs65
- Subassemblies65
- Figure 8: Rear Connection to Terminal Block65
- Main Processor Board66
- Figure 9: Main Processor Board66
- Power Supply Board67
- Figure 10: Power Supply Board67
- Figure 11: Power Supply Assembly68
- Watchdog69
- Figure 12: Power Supply Terminals69
- Rear Serial Port70
- Figure 13: Watchdog Contact Terminals70
- Input Module - 1 Transformer Board71
- Figure 14: Rear Serial Port Terminals71
- Figure 15: Input Module - 1 Transformer Board71
- Input Module Circuit Description72
- Figure 16: Input Module Schematic72
- Transformer Board73
- Figure 17: Transformer Board73
- Input Board74
- Figure 18: Input Board74
- Standard Output Relay Board75
- Figure 19: Standard Output Relay Board - 8 Contacts75
- IRIG-B Board76
- Figure 20: IRIG-B Board76
- Fibre Optic Board77
- Figure 21: Fibre Optic Board77
- Rear Communication Board78
- Ethernet Board78
- Figure 22: Rear Communication Board78
- Figure 23: Ethernet Board78
- Redundant Ethernet Board80
- Figure 24: Redundant Ethernet Board80
Chapter 4 Software Design83
Chapter Overview85
Sofware Design Overview86
- Figure 25: Software Architecture86
System Level Software87
- Real Time Operating System87
- System Services Software87
- Self-Diagnostic Software87
- Startup Self-Testing87
- System Boot87
- System Level Software Initialisation88
- Platform Software Initialisation and Monitoring88
- Continuous Self-Testing88
Platform Software89
- Record Logging89
- Settings Database89
- Interfaces89
Protection and Control Functions90
- Acquisition of Samples90
- Frequency Tracking90
- Direct Use of Sample Values90
- Fourier Signal Processing90
- Programmable Scheme Logic91
- Figure 26: Frequency Response (Indicative Only)91
- Event Recording92
- Disturbance Recorder92
- Fault Locator92
- Function Key Interface92
Chapter 5 Configuration93
Chapter Overview95
Settings Application Software96
Using the HMI Panel97
- Navigating the HMI Panel98
- Getting Started98
- Figure 27: Navigating the HMI98
- Default Display99
- Default Display Navigation100
- Figure 28: Default Display Navigation100
- Password Entry101
- Processing Alarms and Records101
- Menu Structure102
- Changing the Settings103
- Direct Access (the Hotkey Menu)104
- Setting Group Selection Using Hotkeys104
- Control Inputs104
- Circuit Breaker Control105
- Function Keys105
Date and Time Configuration107
- Using an SNTP Signal107
- Using an IRIG-B Signal107
- Using an IEEE 1588 PTP Signal107
- Without a Timing Source Signal108
- Time Zone Compensation108
- Daylight Saving Time Compensation109
Settings Group Selection110
Chapter 6 Current Protection Functions111
Chapter Overview113
Overcurrent Protection Principles114
- IDMT Characteristics114
- IEC 60255 IDMT Curves115
- European Standards117
- Figure 29: IEC 60255 IDMT Curves117
- North American Standards118
- IEC and IEEE Inverse Curves120
- Figure 30: IEC Standard and very Inverse Curves120
- Figure 31: IEC Extremely Inverse and IEEE Moderate Inverse Curves120
- Differences between the North American and European Standards121
- Programmable Curves121
- Principles of Implementation121
- Figure 32: IEEE very and Extremely Inverse Curves121
- Timer Hold Facility122
- Figure 33: Principle of Protection Function Implementation122
Phase Overcurrent Protection124
- Phase Overcurrent Protection Implementation124
- Non-Directional Overcurrent Logic125
- Figure 34: Non-Directional Overcurrent Logic Diagram125
- Directional Element126
- Directional Overcurrent Logic127
- Figure 35: Directional Overcurrent Logic Diagram (Phase a Shown Only)127
- Application Notes128
- Parallel Feeders128
- Figure 36: Typical Distribution System Using Parallel Transformers128
- Ring Main Arrangements129
- Setting Guidelines129
- Figure 37: Typical Ring Main with Associated Overcurrent Protection129
- Setting Guidelines (Directional Element)130
Voltage Dependent Overcurrent Element131
- Voltage Dependent Overcurrent Protection Implementation131
- Voltage Controlled Overcurrent Protection131
- Figure 38: Modification of Current Pickup Level for Voltage Controlled Overcurrent Protection131
- Voltage Restrained Overcurrent Protection132
- Figure 39: Modification of Current Pickup Level for Voltage Restrained Overcurrent Protection132
- Voltage Dependent Overcurrent Logic133
- Application Notes133
- Setting Guidelines133
- Figure 40: Voltage Dependant Overcurrent Logic (Phase a to Phase B)133
Current Setting Threshold Selection135
- Figure 41: Selecting the Current Threshold Setting135
Cold Load Pickup136
- Implementation136
- CLP Logic137
- Application Notes137
- CLP for Resistive Loads137
- CLP for Motor Feeders137
- Figure 42: Cold Load Pickup Logic137
- CLP for Switch Onto Fault Conditions138
Selective Logic139
- Selective Logic Implementation139
- Selective Logic Diagram139
- Figure 43: Selective Logic139
Timer Setting Selection141
- Figure 44: Selecting the Timer Settings141
Negative Sequence Overcurrent Protection142
- Negative Sequence Overcurrent Protection Implementation142
- Non-Directional Negative Sequence Overcurrent Logic143
- Composite Earth Fault Start Logic143
- Directional Element143
- Figure 45: Negative Sequence Overcurrent Logic - Non-Directional Operation143
- Figure 46: Composite Earth Fault Start Logic143
- Directional Negative Sequence Overcurrent Logic144
- Application Notes144
- Setting Guidelines (Current Threshold)144
- Figure 47: Negative Sequence Overcurrent Logic - Directional Operation144
- Setting Guidelines (Time Delay)145
- Setting Guidelines (Directional Element)145
Earth Fault Protection146
- Earth Fault Protection Elements146
- Non-Directional Earth Fault Logic147
- IDG Curve147
- Figure 48: Non-Directional EF Logic (Single Stage)147
- Directional Element148
- Residual Voltage Polarisation148
- Figure 49: IDG Characteristic148
- Negative Sequence Polarisation149
- Figure 50: Directional EF Logic with Neutral Voltage Polarization (Single Stage)149
- Application Notes150
- Setting Guidelines (Directional Element)150
- Peterson Coil Earthed Systems150
- Figure 51: Directional Earth Fault Logic with Negative Sequence Polarisation (Single Stage)150
- Figure 52: Current Level (Amps) at Which Transient Faults Are Self-Extinguishing151
- Figure 53: Earth Fault in Petersen Coil Earthed System151
- Figure 54: Distribution of Currents During a Phase C Fault152
- Figure 55: Phasors for a Phase C Earth Fault in a Petersen Coil Earthed System152
- Figure 56: Zero Sequence Network Showing Residual Currents153
- Setting Guidelines (Compensated Networks)154
- Figure 57: Phase C Earth Fault in Petersen Coil Earthed System: Practical Case with Resistance154
Sensitive Earth Fault Protection156
- SEF Protection Implementation156
- Non-Directional SEF Logic156
- Figure 58: Non-Directional SEF Logic156
- SEF any Start Logic157
- EPATR B Curve157
- Figure 59: SEF any Start Logic157
- Directional Element158
- Figure 60: EPATR B Characteristic Shown for TMS = 1.0158
- Figure 61: Types of Directional Control158
- Wattmetric Characteristic159
- Figure 62: Resistive Components of Spill Current159
- Icos Phi / Isin Phi Characteristic160
- Figure 63: Operating Characteristic for Icos160
- Directional SEF Logic161
- Figure 64: Directional SEF with VN Polarisation (Single Stage)161
- Application Notes162
- Insulated Systems162
- Figure 65: Current Distribution in an Insulated System with C Phase Fault162
- Setting Guidelines (Insulated Systems)163
- Figure 66: Phasor Diagrams for Insulated System with C Phase Fault163
- Figure 67: Positioning of Core Balance Current Transformers164
Thermal Overload Protection165
- Single Time Constant Characteristic165
- Dual Time Constant Characteristic165
- Thermal Overload Protection Implementation166
- Thermal Overload Protection Logic166
- Application Notes166
- Setting Guidelines for Dual Time Constant Characteristic166
- Figure 68: Thermal Overload Protection Logic Diagram166
- Figure 69: Spreadsheet Calculation for Dual Time Constant Thermal Characteristic167
- Figure 70: Dual Time Constant Thermal Characteristic167
- Setting Guidelines for Single Time Constant Characteristic168
Broken Conductor Protection170
- Broken Conductor Protection Implementation170
- Broken Conductor Protection Logic170
- Application Notes170
- Setting Guidelines170
- Figure 71: Broken Conductor Logic170
Blocked Overcurrent Protection172
- Blocked Overcurrent Implementation172
- Blocked Overcurrent Logic172
- Blocked Earth Fault Logic172
- Figure 72: Blocked Overcurrent Logic172
- Application Notes173
- Busbar Blocking Scheme173
- Figure 73: Blocked Earth Fault Logic173
- Figure 74: Simple Busbar Blocking Scheme173
- Figure 75: Simple Busbar Blocking Scheme Characteristics174
Second Harmonic Blocking175
- Second Harmonic Blocking Implementation175
- Second Harmonic Blocking Logic (POC Input)176
- Figure 76: 2Nd Harmonic Blocking Logic (POC Input)176
- Second Harmonic Blocking Logic (SEF Input)177
- Application Notes177
- Setting Guidelines177
- Figure 77: 2Nd Harmonic Blocking Logic (SEF Input)177
Load Blinders178
- Load Blinder Implementation178
- Figure 78: Load Blinder and Angle178
- Load Blinder Logic179
- Figure 79: Load Blinder Logic 3Phase179
- Figure 80: Load Blinder Logic Phase a180
Neutral Admittance Protection182
- Neutral Admittance Operation182
- Conductance Operation182
- Figure 81: Admittance Protection182
- Susceptance Operation183
- Figure 82: Conductance Operation183
- Figure 83: Susceptance Operation183
Busbar Protection185
- Figure 84: Simplified Busbar Representation185
- Buswire Supervision186
- Figure 85: High Impedance Differential Protection for Busbars186
Chapter 7 Restricted Earth Fault Protection187
Chapter Overview189
REF Protection Principles190
- Figure 86: REF Protection for Delta Side190
- Figure 87: REF Protection for Star Side190
- Resistance-Earthed Star Windings191
- Solidly-Earthed Star Windings191
- Figure 88: REF Protection for Resistance-Earthed Systems191
- Through Fault Stability192
- Restricted Earth Fault Types192
- Figure 89: REF Protection for Solidly Earthed System192
- Low Impedance REF Principle193
- Figure 90: Low Impedance REF Connection193
- High Impedance REF Principle194
- Figure 91: Three-Slope REF Bias Characteristic194
- Figure 92: High Impedance REF Principle195
- Figure 93: High Impedance REF Connection196
Restricted Earth Fault Protection Implementation197
- Low Impedance REF197
- Setting the Bias Characteristic197
- Delayed Bias198
- Transient Bias198
- High Impedance REF198
- Figure 94: REF Bias Characteristic198
- High Impedance REF Calculation Principles199
Application Notes200
- Star Winding Resistance Earthed200
- Figure 95: Star Winding, Resistance Earthed200
- Low Impedance REF Protection Application201
- Setting Guidelines for Biased Operation201
- Low Impedance REF Scaling Factor201
- Figure 96: Percentage of Winding Protected201
- Parameter Calculations202
- Figure 97: Low Impedance REF Scaling Factor202
- High Impedance REF Protection Application203
- High Impedance REF Operating Modes203
- Figure 98: Hi-Z REF Protection for a Grounded Star Winding203
- Figure 99: Hi-Z REF Protection for a Delta Winding203
- Setting Guidelines for High Impedance Operation204
- Figure 100: Hi-Z REF Protection for Autotransformer Configuration204
- Figure 101: High Impedance REF for the LV Winding205
Chapter 8 CB Fail Protection207
Chapter Overview209
Circuit Breaker Fail Protection210
Circuit Breaker Fail Implementation211
- Circuit Breaker Fail Timers211
- Zero Crossing Detection211
Circuit Breaker Fail Logic213
- Figure 102: Circuit Breaker Fail Logic - Three Phase Start213
- Figure 103: Circuit Breaker Fail Logic - Single Phase Start214
- Figure 104: Circuit Breaker Fail Trip and Alarm215
Undercurrent and ZCD Logic for CB Fail216
- Figure 105: Undercurrent and Zero Crossing Detection Logic for CB Fail216
CB Fail SEF Protection Logic217
- Figure 106: CB Fail SEF Protection Logic217
CB Fail Non Current Protection Logic218
- Figure 107: CB Fail Non Current Protection Logic218
Circuit Breaker Mapping219
- Figure 108: Circuit Breaker Mapping219
Application Notes220
- Reset Mechanisms for CB Fail Timers220
- Setting Guidelines (CB Fail Timer)220
- Setting Guidelines (Undercurrent)221
- Figure 109: CB Fail Timing221
Chapter 9 Current Transformer Requirements223
Chapter Overview225
CT Requirements226
- Phase Overcurrent Protection226
- Directional Elements226
- Non-Directional Elements226
- Earth Fault Protection227
- Directional Elements227
- Non-Directional Elements227
- SEF Protection (Residually Connected)227
- SEF Protection (Core-Balanced CT)228
- Directional Elements228
- Non-Directional Elements228
- Low Impedance REF Protection228
- High Impedance REF Protection228
- High Impedance Busbar Protection229
- Use of Metrosil Non-Linear Resistors229
- Use of ANSI C-Class Cts231
Chapter 10 Voltage Protection Functions233
Chapter Overview235
Undervoltage Protection236
- Undervoltage Protection Implementation236
- Undervoltage Protection Logic237
- Figure 110: Undervoltage - Single and Three Phase Tripping Mode (Single Stage)237
- Application Notes238
- Undervoltage Setting Guidelines238
Overvoltage Protection239
- Overvoltage Protection Implementation239
- Overvoltage Protection Logic240
- Figure 111: Overvoltage - Single and Three Phase Tripping Mode (Single Stage)240
- Application Notes241
- Overvoltage Setting Guidelines241
Rate of Change of Voltage Protection242
- Rate of Change of Voltage Protection Implementation242
- Rate of Change of Voltage Logic242
- Figure 112: Rate of Change of Voltage Protection Logic242
Residual Overvoltage Protection244
- Residual Overvoltage Protection Implementation244
- Residual Overvoltage Logic245
- Application Notes245
- Calculation for Solidly Earthed Systems245
- Figure 113: Residual Overvoltage Logic245
- Calculation for Impedance Earthed Systems246
- Figure 114: Residual Voltage for a Solidly Earthed System246
- Neutral Voltage Displacement (Nvd) Protection Applied to Condenser Bushings (Capacitor Cones)247
- Figure 115: Residual Voltage for an Impedance Earthed System247
- Figure 116: Star Connected Condenser Bushings248
- Figure 117: Theoretical Earth Fault in Condenser Bushing System248
- Figure 118: Condenser Bushing System Vectors249
- Figure 119: Device Connection with Resistors and Shorting Contact250
- Figure 120: Device Connection P141/ P142/ P143/ P145252
- Figure 121: Device Connection P144252
- Setting Guidelines253
Negative Sequence Overvoltage Protection254
- Negative Sequence Overvoltage Implementation254
- Negative Sequence Overvoltage Logic254
- Application Notes254
- Setting Guidelines254
- Figure 122: Negative Sequence Overvoltage Logic254
Sensitive Overvoltage Supervision256
- Sensitive Overvoltage Implementation256
- Sensitive Overvoltage Filter Mode256
- Sensitive Overvoltage Logic257
- Sensitive Overvoltage Operation Logic257
- Figure 123: Sensitive Overvoltage Operation Logic257
- Sensitive Overvoltage Filter Mode Logic258
- Sensitive Overvoltage Blocking Logic258
- Figure 124: Sensitive Overvoltage Filter Mode Logic258
- Figure 125: Sensitive Overvoltage Blocking Logic258
Chapter 11 Frequency Protection Functions259
Chapter Overview261
Frequency Protection Overview262
- Frequency Protection Implementation262
Underfrequency Protection264
- Underfrequency Protection Implementation264
- Underfrequency Protection Logic264
- Figure 126: Underfrequency Logic (Single Stage)264
- Application Notes265
- Setting Guidelines265
Overfrequency Protection266
- Overfrequency Protection Implementation266
- Overfrequency Protection Logic266
- Figure 127: Overfrequency Logic (Single Stage)266
- Application Notes267
- Setting Guidelines267
- Figure 128: Power System Segregation Based Upon Frequency Measurements267
Independent R.O.C.O.F Protection268
- Indepenent R.O.C.O.F Protection Implementation268
- Independent R.O.C.O.F Protection Logic269
- Application Notes269
- Setting Guidelines269
- Figure 129: Independent Rate of Change of Frequency Logic (Single Stage)269
Frequency-Supervised R.O.C.O.F Protection271
- Frequency-Supervised R.O.C.O.F Implementation271
- Frequency-Supervised R.O.C.O.F Logic272
- Application Notes272
- Frequency-Supervised R.O.C.O.F Example272
- Figure 130: Frequency-Supervised Rate of Change of Frequency Logic (Single Stage)272
- Setting Guidelines273
- Figure 131: Frequency Supervised Rate of Change of Frequency Protection273
Average Rate of Change of Frequency Protection274
- Average R.O.C.O.F Protection Implementation274
- Figure 132: Average Rate of Change of Frequency Characteristic274
- Average R.O.C.O.F Logic275
- Application Notes275
- Setting Guidelines275
- Figure 133: Average Rate of Change of Frequency Logic (Single Stage)275
Load Shedding and Restoration277
- Load Restoration Implementation277
- Holding Band277
- Figure 134: Load Restoration with Short Deviation into Holding Band278
- Figure 135: Load Restoration with Long Deviation into Holding Band279
- Load Restoration Logic280
- Application Notes280
- Setting Guidelines280
- Figure 136: Load Restoration Logic280
Chapter 12 Power Protection Functions283
Chapter Overview285
Overpower Protection286
- Overpower Protection Implementation286
- Overpower Logic287
- Application Notes287
- Forward Overpower Setting Guidelines287
- Reverse Power Considerations287
- Figure 137: Overpower Logic287
- Reverse Overpower Setting Guidelines288
Underpower Protection289
- Underpower Protection Implementation289
- Underpower Logic290
- Application Notes290
- Low Forward Power Considerations290
- Low Forward Power Setting Guidelines290
- Figure 138: Underpower Logic290
Sensitive Power Protection292
- Sensitive Power Protection Implementation292
- Sensitive Power Measurements292
- Sensitive Power Logic293
- Application Notes293
- Sensitive Power Calculation293
- Figure 139: Sensitive Power Logic Diagram293
- Figure 140: Sensitive Power Input Vectors294
- Sensitive Power Setting Guidelines295
Transient Earth Fault Detection296
- Transient Earth Fault Detection Implementation297
- Transient Earth Fault Detector297
- Fault Type Detector297
- Direction Detector297
- Transient Earth Fault Detection Logic298
- Transient Earth Fault Detection Logic Overview298
- Figure 141: Transient Earth Fault Logic Overview298
- Fault Type Detector Logic299
- Direction Detector Logic - Standard Mode299
- Transient Earth Fault Detection Output Alarm Logic299
- Figure 142: Fault Type Detector Logic299
- Figure 143: Direction Detector Logic - Standard Mode299
- Figure 144: TEFD Output Alarm Logic299
Chapter 13 Autoreclose301
Chapter Overview303
Introduction to 3-Phase Autoreclose304
Implementation305
Autoreclose Function Inputs306
- CB Healthy306
- Block AR306
- Reset Lockout306
- AR Auto Mode306
- Auto Mode306
- Liveline Mode306
- Telecontrol Mode306
- Circuits OK306
- AR Sys Checks OK307
- Ext AR Prot Trip (External AR Protection Trip)307
- Ext AR Prot Start (External AR Protection Start)307
- DAR Complete (Delayed Autoreclose Complete)307
- CB in Service (Circuit Breaker in Service)307
- AR Restart307
- DT OK to Start (Dead Time OK to Start)307
- Deadtime Enabled308
- AR Init Triptest (Initiate Trip Test)308
- AR Skip Shot308
- Inh Reclaim Time (Inhibit Reclaim Time)308
Autoreclose Function Outputs309
- AR in Progress309
- AR in Progress 1 (DAR in Progress)309
- Sequence Counter Status DDB Signals309
- Successful Close309
- AR in Service309
- Block Main Prot (Block Main Protection)309
- Block SEF Prot (Block SEF Protection)309
- Reclose Checks309
- Deadt in Prog (Dead Time in Progress)310
- DT Complete (Dead Time Complete)310
- AR Sync Check (AR Synchronisation Check)310
- AR Syschecks OK (AR System Checks OK)310
- Auto Close310
- Protection Lockt (Protection Lockout)310
- Reset Lckout Alm (Reset Lockout Alarm)310
- Reclaim in Prog310
- Reclaim Complete310
Autoreclose Function Alarms311
- AR no Sys Check311
- AR CB Unhealthy311
- AR Lockout311
Autoreclose Operation312
- Operating Modes313
- Four-Position Selector Switch Implementation313
- Figure 145: Four-Position Selector Switch Implementation314
- Operating Mode Selection Logic315
- Autoreclose Initiation315
- Figure 146: Autoreclose Mode Select Logic315
- Start Signal Logic317
- Trip Signal Logic317
- Figure 147: Start Signal Logic317
- Figure 148: Trip Signal Logic317
- Blocking Signal Logic318
- Shots Exceeded Logic318
- Figure 149: Blocking Signal Logic318
- Figure 150: Shots Exceeded Logic318
- AR Initiation Logic319
- Blocking Instantaneous Protection for Selected Trips319
- Figure 151: AR Initiation Logic319
- Figure 152: Blocking Instantaneous Protection for Selected Trips320
- Blocking Instantaneous Protection for Lockouts321
- Dead Time Control322
- Figure 153: Blocking Instantaneous Protection for Lockouts322
- AR CB Close Control323
- Figure 154: Dead Time Control Logic323
- AR System Checks324
- Figure 155: AR CB Close Control Logic324
- Reclaim Timer Initiation325
- Figure 156: AR System Check Logic325
- Autoreclose Inhibit326
- Figure 157: Reclaim Time Logic326
- Autoreclose Lockout327
- Figure 158: AR Initiation Inhibit327
- Figure 159: Overall Lockout Logic328
- Sequence Co-Ordination329
- Figure 160: Lockout for Protection Trip When AR Is Not Available329
- System Checks for First Reclose330
Setting Guidelines331
- Number of Shots331
- Dead Timer Setting331
- Stability and Synchronism Requirements331
- Operational Convenience331
- Load Requirements332
- Circuit Breaker332
- Fault De-Ionisation Time332
- Protection Reset Time332
- Reclaim Timer Setting333
Chapter 14 Monitoring and Control335
Chapter Overview337
Event Records338
- Event Types338
- Opto-Input Events339
- Contact Events339
- Alarm Events339
- Fault Record Events340
- Maintenance Events340
- Protection Events340
- Figure 161: Fault Recorder Stop Conditions340
- Security Events341
- Platform Events341
Disturbance Recorder342
Measurements343
- Measured Quantities343
- Measured and Calculated Currents343
- Measured and Calculated Voltages343
- Power and Energy Quantities343
- Demand Values344
- Frequency Measurements344
- Other Measurements344
- Measurement Setup344
- Fault Locator345
- Fault Locator Settings Example345
- Opto-Input Time Stamping345
CB Condition Monitoring346
- Application Notes346
- Setting the Thresholds for the Total Broken Current346
- Setting the Thresholds for the Number of Operations346
- Setting the Thresholds for the Operating Time347
- Setting the Thresholds for Excesssive Fault Frequency347
CB State Monitoring348
- CB State Monitoring Logic349
- Figure 162: CB State Monitoring Logic349
Circuit Breaker Control350
- CB Control Using the IED Menu350
- CB Control Using the Hotkeys351
- CB Control Using the Function Keys351
- Figure 163: Hotkey Menu Navigation351
- CB Control Using the Opto-Inputs352
- Remote CB Control352
- Figure 164: Default Function Key PSL352
- Figure 165: Remote Control of Circuit Breaker353
- CB Control Logic354
- Synchronisation Check354
- CB Healthy Check354
- Figure 166: CB Control Logic354
Pole Dead Function355
- Pole Dead Logic355
- Figure 167: Pole Dead Logic355
System Checks356
- System Checks Implementation356
- VT Connections356
- Voltage Monitoring356
- Check Synchronisation357
- Check Syncronisation Vector Diagram357
- System Split358
- Figure 168: Check Synchronisation Vector Diagram358
- System Check Logic359
- Figure 169: System Check Logic359
- System Check PSL360
- Application Notes360
- Slip Control360
- Figure 170: System Check PSL360
- Use of Check Sync 2 and System Split361
- Predictive Closure of Circuit Breaker361
- Voltage and Phase Angle Correction361
Switch Status and Control363
- Figure 171: Representation of Typical Feeder Bay363
- Switch Status Logic364
- Figure 172: Switch Status Logic364
- Switch Control Logic365
- Figure 173: Switch Control Logic365
Chapter 15 Supervision367
Chapter Overview369
Voltage Transformer Supervision370
- Loss of One or Two Phase Voltages370
- Loss of All Three Phase Voltages370
- Absence of All Three Phase Voltages on Line Energisation370
- VTS Implementation371
- VTS Logic371
- Figure 174: VTS Logic372
- VTS Acceleration Indication Logic373
- Figure 175: VTS Acceleration Indication Logic373
Current Transformer Supervision374
- CTS Implementation374
- CTS Logic374
- Figure 176: CTS Logic Diagram374
- Application Notes375
- Setting Guidelines375
Trip Circuit Supervision376
- Trip Circuit Supervision Scheme376
- Resistor Values376
- Psl for Tcs Scheme 1377
- Trip Circuit Supervision Scheme 2377
- Figure 177: TCS Scheme378
- Figure 178: PSL for TCS Scheme378
- Figure 179: TCS Scheme378
- Figure 180: PSL for TCS Scheme 2378
- Figure 181: TCS Scheme 3379
- Figure 182: PSL for TCS Scheme 3379
Chapter 16 Digital I/O and PSL Configuration381
Chapter Overview383
Configuring Digital Inputs and Outputs384
Scheme Logic385
- Figure 183: Scheme Logic Interfaces385
- PSL Editor386
- PSL Schemes386
- PSL Scheme Version Control386
Configuring the Opto-Inputs387
Assigning the Output Relays388
Fixed Function Leds389
- Trip LED Logic389
- Figure 184: Trip LED Logic389
Configuring Programmable Leds390
Function Keys392
Control Inputs393
Chapter 17 Electrical Teleprotection395
Chapter Overview397
Introduction398
Teleprotection Scheme Principles399
- Direct Tripping399
- Permissive Tripping399
Implementation400
Configuration401
- Figure 185: Example Assignment of Intermicom Signals Within the PSL402
Connecting to Electrical Intermicom403
- Short Distance403
- Long Distance403
- Figure 186: Direct Connection403
- Figure 187: Indirect Connection Using Modems403
Application Notes404
Chapter 18 Communications407
Chapter Overview409
Communication Interfaces410
Serial Communication411
- EIA(RS)232 Bus411
- EIA(RS)485 Bus411
- EIA(RS)485 Biasing Requirements412
- K-Bus412
- Figure 188: RS485 Biasing Circuit412
- Figure 189: Remote Communication Using K-Bus413
Standard Ethernet Communication414
- Hot-Standby Ethernet Failover414
Redundant Ethernet Communication415
- Supported Protocols415
- Parallel Redundancy Protocol416
- Figure 190: IED Attached to Separate Lans416
- PRP Application in the Substation417
- High-Availability Seamless Redundancy (HSR)417
- HSR Multicast Topology417
- Figure 191: PRP Application in the Substation417
- HSR Unicast Topology418
- Figure 192: HSR Multicast Topology418
- HSR Application in the Substation419
- Figure 193: HSR Unicast Topology419
- Rapid Spanning Tree Protocol420
- Figure 194: HSR Application in the Substation420
- Figure 195: IED Attached to Redundant Ethernet Star or Ring Circuit420
- Self Healing Protocol421
- Figure 196: IED, Bay Computer and Ethernet Switch with Self Healing Ring Facilities421
- Figure 197: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches421
- Dual Homing Protocol422
- Figure 198: Redundant Ethernet Ring Architecture with IED, Bay Computer and Ethernet Switches422
- Figure 199: Dual Homing Mechanism423
- Configuring IP Addresses424
- Figure 200: Application of Dual Homing Star at Substation Level424
- Configuring the IED IP Address425
- Configuring the REB IP Address425
- Figure 201: IED and REB IP Address Configuration425
Simple Network Management Protocol (SNMP)429
- SNMP Management Information Bases429
- Main Processor MIBS Structure429
- Redundant Ethernet Board MIB Structure430
- Accessing the MIB434
- Main Processor SNMP Configuration434
Data Protocols436
- Courier436
- Physical Connection and Link Layer436
- Courier Database437
- Settings Categories437
- Setting Changes437
- Event Extraction437
- Disturbance Record Extraction439
- Programmable Scheme Logic Settings439
- Time Synchronisation439
- Courier Configuration440
- Physical Connection and Link Layer441
- Iec 60870-5-103441
- Initialisation442
- Time Synchronisation442
- Spontaneous Events442
- General Interrogation (GI)442
- Cyclic Measurements442
- Commands442
- Test Mode443
- Disturbance Records443
- Command/Monitor Blocking443
- IEC 60870-5-103 Configuration443
- Dnp444
- Physical Connection and Link Layer445
- Object 1 Binary Inputs445
- Object 10 Binary Outputs445
- Object 20 Binary Counters446
- Object 30 Analogue Input446
- Figure 202: Control Input Behaviour446
- Object 40 Analogue Output447
- Object 50 Time Synchronisation447
- DNP3 Device Profile447
- DNP3 Configuration455
- Modbus456
- Physical Connection and Link Layer457
- MODBUS Functions457
- Response Codes457
- Register Mapping458
- Event Extraction458
- Disturbance Record Extraction459
- Figure 203: Manual Selection of a Disturbance Record462
- Figure 204: Automatic Selection of Disturbance Record - Method 1463
- Figure 205: Automatic Selection of Disturbance Record - Method 2464
- Figure 206: Configuration File Extraction465
- Figure 207: Data File Extraction466
- Setting Changes467
- Password Protection467
- Protection and Disturbance Recorder Settings467
- Time Synchronisation468
- Power and Energy Measurement Data Formats469
- MODBUS Configuration470
- Iec 61850471
- Benefits of IEC 61850471
- IEC 61850 Interoperability472
- The IEC 61850 Data Model472
- Figure 208: Data Model Layers in IEC61850472
- IEC 61850 in Micom Ieds473
- IEC 61850 Data Model Implementation473
- IEC 61850 Communication Services Implementation473
- IEC 61850 Peer-To-Peer (GOOSE) Communications474
- Mapping GOOSE Messages to Virtual Inputs474
- Ethernet Functionality474
- IEC 61850 Configuration474
Read Only Mode476
- Courier Protocol Blocking476
- IEC 61850 Protocol Blocking477
- Read-Only Settings477
- Read-Only DDB Signals477
Time Synchronisation478
- Demodulated IRIG-B478
- Figure 209: GPS Satellite Timing Signal478
- IRIG-B Implementation479
- Sntp479
- Loss of SNTP Server Signal Alarm479
- IEEE 1588 Precision Time Protocol479
- Accuracy and Delay Calculation479
- PTP Domains480
- Time Synchronsiation Using the Communication Protocols480
- Figure 210: Timing Error Using Ring or Line Topology480
Chapter 19 Cyber-Security481
Overview483
The Need for Cyber-Security484
Standards485
- NERC Compliance485
- Cip 002486
- Cip 007487
- Ieee 1686-2007487
Cyber-Security Implementation489
- NERC-Compliant Display489
- Four-Level Access490
- Figure 211: Default Display Navigation490
- Blank Passwords491
- Password Rules491
- Access Level Ddbs492
- Enhanced Password Security492
- Password Strengthening492
- Password Validation492
- Password Blocking493
- Password Recovery494
- Password Encryption495
- Disabling Physical Ports495
- Disabling Logical Ports495
- Security Events Management496
- Logging out498
Chapter 20 Installation499
Chapter Overview501
Handling the Goods502
- Receipt of the Goods502
- Unpacking the Goods502
- Storing the Goods502
- Dismantling the Goods502
Mounting the Device503
- Flush Panel Mounting503
- Figure 212: Location of Battery Isolation Strip503
- Rack Mounting504
- Figure 213: Rack Mounting of Products504
Cables and Connectors506
- Terminal Blocks506
- Figure 214: Terminal Block Types506
- Power Supply Connections507
- Earth Connnection507
- Current Transformers507
- Voltage Transformer Connections508
- Watchdog Connections508
- EIA(RS)485 and K-Bus Connections508
- IRIG-B Connection508
- Opto-Input Connections508
- Output Relay Connections508
- Ethernet Metallic Connections509
- Ethernet Fibre Connections509
- RS232 Connection509
- Download/Monitor Port509
- GPS Fibre Connection509
- Fibre Communication Connections509
Case Dimensions510
- Case Dimensions 40TE510
- Figure 215: 40TE Case Dimensions510
- Case Dimensions 60TE511
- Figure 216: 60TE Case Dimensions511
- Case Dimensions 80TE512
- Figure 217: 80TE Case Dimensions512
Chapter 21 Commissioning Instructions513
Chapter Overview515
General Guidelines516
Commissioning Test Menu517
- Opto I/P Status Cell (Opto-Input Status)517
- Relay O/P Status Cell (Relay Output Status)517
- Test Port Status Cell517
- Monitor Bit 1 to 8 Cells517
- Test Mode Cell518
- Test Pattern Cell518
- Contact Test Cell518
- Test Leds Cell518
- Test Autoreclose Cell518
- Red and Green LED Status Cells519
- Using a Monitor Port Test Box519
Commissioning Equipment520
- Recommended Commissioning Equipment520
- Essential Commissioning Equipment520
- Advisory Test Equipment521
Product Checks522
- Product Checks with the IED De-Energised522
- Visual Inspection523
- Current Transformer Shorting Contacts523
- Insulation523
- External Wiring523
- Watchdog Contacts524
- Power Supply524
- Product Checks with the IED Energised524
- Test LCD525
- Date and Time525
- Test Leds526
- Test Alarm and Out-Of-Service Leds526
- Test Trip LED526
- Test User-Programmable Leds526
- Test Opto-Inputs526
- Test Output Relays526
- Test Serial Communication Port RP1527
- Figure 218: RP1 Physical Connection527
- Test Serial Communication Port RP2528
- Test Ethernet Communication528
- Figure 219: Remote Communication Using K-Bus528
- Secondary Injection Tests529
- Test Current Inputs529
- Test Voltage Inputs529
Setting Checks531
- Apply Application-Specific Settings531
- Transferring Settings from a Settings File531
- Entering Settings Using the HMI531
Protection Timing Checks533
- Overcurrent Check533
- Connecting the Test Circuit533
- Performing the Test533
- Check the Operating Time533
Onload Checks535
- Confirm Current Connections535
- Confirm Voltage Connections535
- On-Load Directional Test536
Final Checks537
Chapter 22 Maintenance and Troubleshooting539
Chapter Overview541
Maintenance542
- Maintenance Checks542
- Alarms542
- Opto-Isolators542
- Output Relays542
- Measurement Accuracy542
- Replacing the Device543
- Repairing the Device544
- Removing the Front Panel544
- Figure 220: Possible Terminal Block Types544
- Replacing Pcbs545
- Replacing the Main Processor Board545
- Replacement of Communications Boards546
- Figure 221: Front Panel Assembly546
- Replacement of the Input Module547
- Replacement of the Power Supply Board547
- Replacement of the I/O Boards548
- Recalibration548
- Changing the Battery548
- Post Modification Tests549
- Battery Disposal549
- Cleaning549
Troubleshooting550
- Self-Diagnostic Software550
- Power-Up Errors550
- Error Message or Code on Power-Up550
- Out of Service LED on at Power-Up551
- Error Code During Operation552
- Backup Battery552
- Mal-Operation During Testing552
- Failure of Output Contacts552
- Failure of Opto-Inputs552
- Incorrect Analogue Signals553
- PSL Editor Troubleshooting553
- Diagram Reconstruction553
- PSL Version Check553
Repair and Modification Procedure554
Chapter 23 Technical Specifications555
Chapter Overview557
Interfaces558
- Front Serial Port558
- Download/Monitor Port558
- Rear Serial Port558
- Fibre Rear Serial Port558
- Optional Rear Serial Port (SK5)559
- IRIG-B (Demodulated)559
- IRIG-B (Modulated)559
- Rear Serial Port 2559
- Rear Ethernet Port Copper560
- Rear Ethernet Port Fibre560
- 100 Base Fx Receiver Characteristics560
- 100 Base Fx Transmitter Characteristics561
Performance of Current Protection Functions562
- Transient Overreach and Overshoot562
- Phase Overcurrent Protection562
- Phase Overcurrent Directional Parameters562
- Voltage Dependent Overcurrent Protection562
- Earth Fault Protection563
- Earth Fault Directional Parameters563
- Sensitive Earth Fault Protection564
- SEF Directional Parameters564
- Restricted Earth Fault Protection564
- Negative Sequence Overcurrent Protection565
- NPSOC Directional Parameters565
- Circuit Breaker Fail and Undercurrent Protection565
- Broken Conductor Protection565
- Thermal Overload Protection565
- Cold Load Pickup Protection566
- Selective Overcurrent Protection566
- Voltage Dependent Overcurrent Protection566
- Neutral Admittance Protection566
Performance of Voltage Protection Functions567
- Undervoltage Protection567
- Overvoltage Protection567
- Residual Overvoltage Protection567
- Negative Sequence Voltage Protection567
- Rate of Change of Voltage Protection568
Performance of Frequency Protection Functions569
- Basic Overfrequency Protection569
- Basic Underfrequency Protection569
- Advanced Overfrequency Protection569
- Advanced Underfrequency Protection570
- Supervised Rate of Change of Frequency Protection570
- Independent Rate of Change of Frequency Protection570
- Average Rate of Change of Frequency Protection571
- Load Restoration571
Power Protection Functions572
- Overpower / Underpower Protection572
- Sensitive Power Protection572
Performance of Monitoring and Control Functions573
- Voltage Transformer Supervision573
- Standard Current Transformer Supervision573
- CB State and Condition Monitoring573
- PSL Timers573
Measurements and Recording574
- General574
- Disturbance Records574
- Event, Fault and Maintenance Records574
- Fault Locator574
Ratings575
- AC Measuring Inputs575
- Current Transformer Inputs575
- Voltage Transformer Inputs575
- Auxiliary Supply Voltage575
- Nominal Burden576
- Power Supply Interruption576
- Battery Backup577
Input / Output Connections578
- Isolated Digital Inputs578
- Nominal Pickup and Reset Thresholds578
- Standard Output Contacts578
- High Break Output Contacts579
- Watchdog Contacts579
Mechanical Specifications580
- Physical Parameters580
- Enclosure Protection580
- Mechanical Robustness580
- Transit Packaging Performance580
Type Tests581
- Insulation581
- Creepage Distances and Clearances581
- High Voltage (Dielectric) Withstand581
- Impulse Voltage Withstand Test581
Environmental Conditions582
- Ambient Temperature Range582
- Temperature Endurance Test582
- Ambient Humidity Range582
- Corrosive Environments582
Electromagnetic Compatibility583
- Mhz Burst High Frequency Disturbance Test583
- Damped Oscillatory Test583
- Immunity to Electrostatic Discharge583
- Electrical Fast Transient or Burst Requirements583
- Surge Withstand Capability583
- Surge Immunity Test584
- Immunity to Radiated Electromagnetic Energy584
- Radiated Immunity from Digital Communications584
- Radiated Immunity from Digital Radio Telephones584
- Immunity to Conducted Disturbances Induced by Radio Frequency Fields584
- Magnetic Field Immunity585
- Conducted Emissions585
- Radiated Emissions585
- Power Frequency585
Regulatory Compliance586
- EMC Compliance: 2014/30/EU586
- LVD Compliance: 2014/35/EU586
- R&TTE Compliance: 2014/53/EU586
- UL/CUL Compliance586
- ATEX Compliance: 2014/34/EU586
Appendix A Ordering Options589
Appendix B Settings and Signals591
Appendix C Wiring Diagrams599

Brand	GE
Model	MiCOM P145 Agile
Category	Control Unit
Language	English

GE MiCOM P145 Agile User Manual

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GE MiCOM P145 Agile Specifications

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