If the signal is correctly applied, this indicates failure of an opto-input, which may be situated on standalone opto-
input board, or on an opto-input boar
d that is part of the input module. Separate opto-input boards can simply be
replaced. If, however, the faulty opto-input board is part of the input module, the complete input module should be
replaced. This is because the analogue input module cannot be individually replaced without dismantling the
module and recalibration of the IED.
3.6.3 INCORRECT ANALOGUE SIGNALS
If the measured analogue quantities do not seem correct, use the measurement function to determine the type of
pr
oblem. The measur
ements can be configured in primary or secondary terms.
1. Compare the displayed measured values with the actual magnitudes at the terminals.
2. Check the correct terminals are used.
3. Check the CT and VT ratios set are correct.
4. Check the phase displacement to confirm the inputs are correctly connected.
3.7 PSL EDITOR TROUBLESHOOTING
A failure to open a connection could be due to one or more of the following:
● The IED address is not v
alid (this address is always 1 for the front port)
● Password in not valid
● Communication set-up (COM port, Baud rate, or Framing) is not correct
● Transaction values are not suitable for the IED or the type of connection
● The connection cable is not wired correctly or broken
● The option switches on any protocol converter used may be incorrectly set
3.7.1 DIAGRAM RECONSTRUCTION
Although a scheme can be extracted from an IED, a facility is provided to recover a scheme if the original file is
unobtainable.
A r
ecov
ered scheme is logically correct but much of the original graphical information is lost. Many signals are
drawn in a vertical line down the left side of the canvas. Links are drawn orthogonally using the shortest path from
A to B. Any annotation added to the original diagram such as titles and notes are lost.
Sometimes a gate type does not appear as expected. For example, a single-input AND gate in the original scheme
appears as an OR gate when uploaded. Programmable gates with an inputs-to-trigger value of 1 also appear as
OR gates
3.7.2 PSL VERSION CHECK
The PSL is saved with a version reference, time stamp and CRC check (Cyclic Redundancy Check). This gives a
visual check whether the default PSL is in place or whether a new application has been downloaded.
P14x Chapter 22 - Maintenance and Troubleshooting
P14xEd1-TM-EN-1 527
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