14-14 Status Structure
Measurement Event Register
The used bits of the Measurement Event Register (shown in Figure 14-6) are described as
follows:
• Bit B0, Limit 1 Fail (L1) — Set bit indicates that the Limit 1 test has failed.
• Bit B1, Low Limit 2 Fail (LL2) — Set bit indicates that the Low Limit 2 test has failed.
• Bit B2, High Limit 2 Fail (HL2) — Set bit indicates that the High Limit 2 test has
failed.
• Bit B3, Low Limit 3 Fail (LL3) — Set bit indicates that the Low Limit 3 test has failed.
• Bit B4, High Limit 3 Fail (HL3) — Set bit indicates that the High Limit 3 test has
failed.
• Bit B5, Limits Pass (LP) — Set bit indicates that all limit tests passed.
• Bit B6, Reading Available (RAV) — Set bit indicates that a reading was taken and
processed.
• Bit B7, Reading Overflow (ROF) — Set bit indicates that the volts or amps reading
exceeds the selected measurement range of the SourceMeter.
• Bit B8, Buffer Available (BAV) — Set bit indicates that there are at least two readings
in the buffer.
• Bit B9, Buffer Full (BFL) — Set bit indicates that the trace buffer is full.
• Bit B10 — Not used.
• Bit B11, Interlock Asserted (Int) — Set bit indicates that the interlock line is at digital
low (asserted). The source output can be turned on.
• Bit B12, Over Temperature (OT) — Set bit indicates that an over temperature condi-
tion exists. The source output cannot be turned on.
• Bit B13, Over Voltage Protection (OVP) — Set bit indicates that the source is being
limited at the programmed limit level.
• Bit B14, Compliance (Comp) — Set bit indicates that the source is in compliance.
• Bit B15 — Not used.
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